Pin Assignment

Pin Description

Pin Name

I/O

Options

Description

PA0~PA2

PA3/PFD

PA4/TMR

PA5/INT

PA6, PA7

I/O

Pull-high

Wake-up

PA3 or PFD

Bidirectional 8-bit input/output port. Each bit can be configured as wake-up

input by options. Software instructions determine the CMOS output or Schmitt

trigger input with or without pull-high resistor (determined by pull-high options: bit

option). The PFD, TMR and INT are pin-shared with PA3, PA4 and PA5, re-

spectively.

PB0/AN0

PB1/AN1

PB2/AN2

PB3/AN3

I/O

Pull-high

Bidirectional 4-bit input/output port. Software instructions determine the

CMOS output, Schmitt trigger input with or without pull-high resistor (deter-

mined by pull-high options: bit option) or A/D input.

Once a PB line is selected as an A/D input (by using software control), the I/O

function and pull-high resistor are disabled automatically.

PD0/PWM

I/O

Pull-high

PD0 or PWM

Bidirectional I/O line. Software instructions determine the CMOS output,

Schmitt trigger input with or without a pull-high resistor (determined by

pull-high options: bit option). The PWM output function is pin-shared with

PD0 (dependent on PWM options).

RES

I

¾

Schmitt trigger reset input. Active low.

VDD

¾¾

Positive power supply

VSS

¾¾

Negative power supply, ground.

OSC1

OSC2

I

O

Crystal

or RC

OSC1, OSC2 are connected to an RC network or a Crystal (determined by

options) for the internal system clock. In the case of RC operation, OSC2 is

the output terminal for 1/4 system clock.

Absolute Maximum Ratings

Storage Temperature ............................

-50°Cto125°C

Operating Temperature...........................

-40°Cto85°C

Note: These are stress ratings only. Stresses exceeding the range specified under

²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

HT46R46/HT46C46/HT46R47/HT46C47

Rev. 1.00

3

December 28, 2004

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P D 0 / P W M

P A 3 / P F D

P A 2

P A 1

P A 0

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

V S S

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

1

2

3

4

5

6

7

8

9

H T 4 6 R 4 6 / H T 4 6 C 4 6

H T 4 6 R 4 7 / H T 4 6 C 4 7

1 8 D I P - A / S O P - A