HT46R46 datasheet(17/42 Pages) HOLTEK

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HT46R46/HT46C46/HT46R47/HT46C47

Rev. 1.00

December 28, 2004

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H and 19H.

After a chip reset, these input/output lines remain at high

levels or floating state (dependent on pull-high options).

Each bit of these input/output latches can be set or

cleared by

²SET [m].i² and ²CLR [m].i² (m=12H, 14H or

18H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. The highest 4-bit of port B and 7 bits of port D

are not physically implemented; on reading them a

²0² is

returned whereas writing then results in a no-operation.

See Application note.

Each I/O line has a pull-high option. Once the pull-high

option is selected, the I/O line has a pull-high resistor,

otherwise, there

¢s none. Take note that a non-pull-high

I/O line operating in input mode will cause a floating

state.

The PA3 is pin-shared with the PFD signal. If the PFD

option is selected, the output signal in output mode of

PA3 will be the PFD signal generated by the timer/event

counter overflow signal. The input mode always remain-

ing its original functions. Once the PFD option is se-

lected, the PFD output signal is controlled by PA3 data

²1² to PA3 data register will enable

the PFD output function and writing

²0² will force the

PA3 to remain at

²0². The I/O functions of PA3 are

shown below.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PFD)

O/P

(PFD)

PA3

Logical

Input

Logical

Output

Logical

Input

PFD

(Timer on)

Note:

The PFD frequency is the timer/event counter

overflow frequency divided by 2.

The PA5 and PA4 are pin-shared with INT and TMR pins

respectively.

The PB can also be used as A/D converter inputs. The

A/D function will be described later. There is a PWM

function shared with PD0. If the PWM function is en-

abled, the PWM signal will appear on PD0 (if PD0 is op-

erating in output mode). Writing

²1² to PD0 data register

will enable the PWM output function and writing

²0² will

force the PD0 to remain at

²0². The I/O functions of PD0

are as shown.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PWM)

O/P

(PWM)

PD0

Logical

Input

Logical

Output

Logical

Input

PWM

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

PWM

The microcontroller provides 1 channel (6+2) bits PWM

output shared with PD0. The PWM channel has its data

of the PWM counter comes from fSYS. The PWM register

is an eight bits register. The waveforms of PWM output

are as shown. Once the PD0 is selected as the PWM

output and the output function of PD0 is enabled

(PDC.0=

²0²), writing 1 to PD0 data register will enable

the PWM output function and writing

²0² will force the

PD0 to stay at

²0².

A PWM cycle is divided into four modulation cycles

(modulation cycle 0~modulation cycle 3). Each modula-

tion cycle has 64 PWM input clock period. In a (6+2) bit

PWM function, the contents of the PWM register is di-

vided into two groups. Group 1 of the PWM register is

denoted by DC which is the value of PWM.7~PWM.2.

The group 2 is denoted by AC which is the value of

PWM.1~PWM.0.

In a PWM cycle, the duty cycle of each modulation cycle

is shown in the table.

Parameter

AC (0~3)

Duty Cycle

Modulation cycle i

(i=0~3)

i<AC

DC+1

³AC

The modulation frequency, cycle frequency and cycle

duty of the PWM output signal are summarized in the

following table.

PWM

Modulation

Frequency

PWM Cycle

Frequency

PWM Cycle

Duty

fSYS/64

fSYS/256

[PWM]/256

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