HT46R46 datasheet(16/42 Pages) HOLTEK

16 / 42 page

HT46R46/HT46C46/HT46R47/HT46C47

Rev. 1.00

December 28, 2004

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register will also

reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow

occurs. When the timer/event counter (reading TMR) is

read, the clock will be blocked to avoid errors. As clock

blocking may results in a counting error, this must be

taken into consideration by the programmer.

The bit0~bit2 of the TMRC can be used to define the

pre-scaling stages of the internal clock sources of

timer/event counter. The definitions are as shown. The

overflow signal of timer/event counter can be used to

generate the PFD signal.

Input/Output Ports

There are 13 bidirectional input/output lines in the

microcontroller, labeled as PA, PB and PD, which are

mapped to the data memory of [12H], [14H] and [18H]

respectively. All of these I/O ports can be used for input

and output operations. For input operation, these ports

are non-latching, that is, the inputs must be ready at the

T2 rising edge of instruction

²MOV A,[m]² (m=12H, 14H

or 18H). For output operation, all the data is latched and

remains unchanged until the output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PDC) to control the input/output configuration. With this

control register, CMOS output or Schmitt trigger input

with or without pull-high resistor structures can be re-

configured dynamically (i.e. on-the-fly) under software

control. To function as an input, the corresponding latch

of the control register must write

²1². The input source

also depends on the control register. If the control regis-

ter bit is

²1², the input will read the pad state. If the con-

trol register bit is

²0², the contents of the latches will

move to the internal bus. The latter is possible in the

²read-modify-write² instruction.

V D D

P F D E N

( P A 3 )

W a k e - u p o p t i o n

T M R f o r P A 4 O n l y

I N T f o r P A 5 O n l y

S y s t e m W a k e - u p

( P A o n l y )

R e a d D a t a R e g i s t e r

P A 3

P F D

( P D 0 o r P W M )

C K Q B

C o n t r o l B i t

P U

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P A 0 ~ P A 2

P A 3 / P F D

P A 4 / T M R

P A 5 / I N T

P A 6 , P A 7

P B 0 / A N 0 ~ P B 3 / A N 3

P D 0 / P W M

Input/Output Ports

T M 1

T M 0

T M R

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

8 - B i t T i m e r / E v e n t

C o u n t e r P r e l o a d

R e g i s t e r

8 - B i t T i m e r / E v e n t

C o u n t e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

1 / 2

P F D

8 - s t a g e P r e s c a l e r

8 - 1 M U X

f S Y S

f I N T

P S C 2 ~ P S C 0

( 6 + 2 ) C o m p a r e

P W M

T o P D 0 C i r c u i t

Timer/Event Counter

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