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PIC18LF4520E/SPQTP 数据表(PDF) 102 Page - Microchip Technology |
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PIC18LF4520E/SPQTP 数据表(HTML) 102 Page - Microchip Technology |
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102 / 390 page  PIC18F2420/2520/4420/4520 DS39631A-page 100 Preliminary 2004 Microchip Technology Inc. 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 =High priority 0 = Low priority Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’. bit 6 ADIP: A/D Converter Interrupt Priority bit 1 =High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 =High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit 1 =High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 =High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 =High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 =High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 =High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown |
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