The read/write timing sequences of all the control registers are shown in Fig. 1. The length of the

data is 8-bit wide, therefore, it needs to read and write consecutively twice (MSB 4 bits first then LSB

4 bits). Otherwise, the activation of next ALE will reset the CYCNTR (cycle counter) and it will start

from the MSB 4 bits of next instruction.

ALE

RD_

CS_

Address, 00~08

DATA<7:4>

READ CONTROL REGISTER CYCLE

DATA<3:0>

AD<3:0>

ALE

WR_

CS_

Address, 00~08

DATA<7:4>

WRITE CONTROL REGISTER CYCLE

DATA<3:0>

Next Address

CYCNTR

0

1

2

CYCNTR

0

1

2

AD<3:0>

Interrupt Process

If new data are converted by the ADC and are read by the interface of the microprocessor, that is new event

occurred, this chip activates an interrupt signal through IRQO to the microprocessor to request for accessing.

When the microprocessor receives a negative edge-triggered interrupt signal, the measure register of FS501

has measured new data. The interrupt of the measured event is triggered by signal INTEN (as shown in Table

4).



Table 4. Interrupt Status Register

INSTA

INSTA<1>

INSTA<0>

Event

High speed low resolution AD

conversion

High resolution low speed AD

conversion

INTEN

INTEN<1>

INTEN<0>

Function

Corresponding IRQO enable Corresponding IRQO enable

When the microprocessor is reading data from the measure register, the corresponding interrupt bit is cleared

to 0 to wait for next new measured data.

Interrupt status register, INSTA<0>, is a read-only register. Whereas interrupt enable register, INTEN<0>, is a

read/write register. The read/write timing sequences of these two registers are the same as that of control

registers (as shown in Fig. 1).