Power Low Detector

360K

305K

LBS

CMP

AGND

LBO

ENLBS

BATTERY

9V

VSSD

VBAT

Power low detector is shown in Fig. 6. LBS is the dividing voltage of VBAT and is fed into the input of the power

low detector. The output voltage, LBO, of the power low detector can detect whether the dividing voltage of

VBAT is less than AGND. If it is less than AGND, LBO is high and the user has to replace the battery. Before

reading LBO, we have to set ENLBS to Hi (high), and pull ENLBS to low after approximately 0.1ms; we can

then read LBO.

By the ADC multiplexer, the LBS voltage can be selected by the ADC, and by Equation 1 the LBS voltage can

be found.

Equation 2

LBS

BAT

V

V



 2

.

2

In power saving mode, we can set ENGDR_ (MISC<1>) to high to turn off GNDR to save power consumption.

6.

Clock Generator

Clock Generator

4 MHz

XTALI

XTALO

F

S

1/F

S

OSCO

CLK

DIVIDER

OSCO

1M

ENXTL_

ENOSCO_

FS

FSDIV

The block diagram of the clock generator is shown in Fig. 7. We connect a 4MHz crystal oscillator to the clock

generator to generate a 4MHz clock frequency. A frequency divider is used to divide the clock signal to

generate a signal FS, and the ADC uses this FS signal to do data conversion. FS is controlled by ENXTAL_ and