The interrupt procedures are as follows:

(1) When new data appear in the enabled measure register, IRQO is cleared to 0 and kept in 0.

(2) The microprocessor is activated by the negative edge of IRQO and then reads the contents of the

interrupt status register.

(3) After the read of interrupt status register, IRQO is set to 1.

(4) Check IRQO. If it is not 1, the negative edge signal was not captured, and the microprocessor has to read

the interrupt status register again.

When reading the interrupt register, the negative edge of the new interrupt signal may be lost. Step (4) may

improve this problem. The value of the interrupt status register whether is refreshed or not is independent of

interrupt enable register. The interrupt enable register only affects the IRQO output.

Measure Registers

Table 5. Measure Register

Address

Name

Content

Register Length

Read Times

0E

SUM1<15:0>

Output of low resolution high speed ADC

16

4

0F

SUM1<23:0>

Output of low speed high resolution ADC

24

6

The measure register and the corresponding address of FS501 are shown in Table 5. It is an output for reading

of the microprocessor.

The read timing sequence of the measure register is shown in Fig. 2. The negative edge of IRQC will clear

INSTA<0>. The read count for each read should be correct. Otherwise, the high ALE will clear CYCNTR

(read/write cycle counter) to 0. The read count of the measure register is shown in the last column of Table 5.

When read the measure register, the low of RD_ should be longer than the sampling cycle of the ADC at the

first read cycle. For other read cycles, the low of RD_ can be at least 2us. For example, the sampling rate of the

ADC is 83.3kHz; then the first read cycle for reading the measure register should be greater than 12us.

ALE

RD_

CS_

Address 0F

DATA<3:0>

READ MEASURED REGISTER CYCLE

DATA<N:N-3>

0

1

N/4

CYCNTR

DATA<N-4:N-7>

IRQC

AD<3:0>

2