8.

Analog to Digital Converter (ADC)

The Operation of the Delta-Sigma () Modulator ADC

This high resolution ADC is designed by the technology of delta-sigma () modulator. The continuous analog

signals are sampled by a very high sampling rate that is much higher than the bandwidth of the input signal.

The delta-sigma modulator converts the input signal to a series of 1-bit codes. These 1-bit codes are then fed to

the digital filter to filter out the high frequency quantization noise to find high resolution digital outputs. It can be

used in the high resolution digital multimeters. This kind of ADC quantizes one bit in the analog part, therefore,

it has very good linearity. Because it is in a fully differential configuration, the common mode rejection ratio

(CMRR) is very high and can reduce the common mode signals effectively.

ANALO

G

INTEGRATO

R

DIGITAL LOW PASS

DECIMATION

FILTER

COMPARATOR

ANALO

G

INPU

T

V

in

D

out

1, -1, -1, 1, 1, 1,....

V

DA

C

The symbolic diagram of the delta-sigma ADC is shown in Fig. 10. It consists of an analog subtractor, an

integrator, a comparator, a 1-bit digital-to-analog converter (DAC), and a low-pass digital filter. The analog

signals are continuously sampled and are subtracted by the expected voltage. The difference of the signals is

fed into the integrator, and then the signal is compared with a reference voltage to find a digital output. This

back into the integrator. Due to the infinitive DC gain of the integrator, if the change of the input signal is much

slower than the sampling speed, the average voltage obtained by the delta-sigma modulator will be very close

to the input signal. In some resolution they can be treated to be the same, therefore, the 1-bit output data from

to get a very high resolution digital code.

Gain Stage Setting

0.5

0.5

0.25

0.1

+

ADG<0>

ADG<1>

ADG<2>

ADG<3>

V

IN

to

ADC

signal

input

1.0

0.25

+

ADG<4>

ADG<5>

V

REF

to

ADC

reference

input

a

b

c

d

x

y

There are four different gain paths to the input of the FS501 ADC, and they are controlled by control register

ADG<3:0>; the block diagram is shown in Fig. 11. Two different gain paths control the input reference voltage,

and they are controlled by control register ADG<5:4>. The gains shown here are not accurate. The accurate

gains can be found by careful calibration.