GPCE2P064B datasheet(12/25 Pages) GENERALPLUS

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GPCE2P064B

Proprietary & Confidential

Apr. 07, 2015

Version: 1.2

key wakeup port.

To activate key wakeup function, latch data on

Port_IOA_Data and enable the key wakeup function.

Wakeup is

triggered when the PortA state is different from at the time

latched.

Furthermore, the I/O ports can be operated at 5V level,

higher than the CPU core which is a 3V level system.

Suppose

system operating voltage is running at 3.3V, VDDIO (power for

I/O) operates from 3.3V to 5.5V.

In such condition, the I/O pad

is capable of operating from 0V through VDDIO.

The following

diagram is an I/O schematic.

Although data can be written into

the same register through Port_Data and Port_Buffer, they can

be read from different places, Buffer (R) and Data (R).

Control

logic

pull high

pull low

Pin pad

Buffer(R)

Data(R)

Port_Data(W)

Port_Buffer(W)

Port_DIR(R/W)

Port_ATTR(R/W)

In addition to a general purpose I/O port function, PortA/B also

shares/carries some special functions.

6.8 Timer / Counter

GPCE2P064B provides three 16-bit timers/counters - TimerA,

TimerB and TimerC or so called universal counters.

The clock

source of Timer A/B/C are from clock source Input 1 and clock

source Input 2 (see below table) which perform AND operation to

form the varieties of combinations.

When timer overflows, a

timeout signal (TAOUT) is sent to CPU interrupt module to

generate a timer interrupt signal.

In addition, Timer A/B/C

hardware interrupt events can be used to latch the DAC audio

output and trigger ADC conversion.

6.9 IO PWM

One IO PWMs which duty is selected from 1/256 to 254/256.

Example the below figure is a 3/256-duration cycle.

The PWMO

waveform

made

selecting

pulse

width

through

Port_PWM_Ctrl.

As a result, each 256 cycles will generate a

pulse width defined in control port.

These PWM signals can be

applied for controlling the speed of motor or other devices.

Tpwmo

Tduty

PWMO

TimerA_Timeout

...

251

252

253

254

255

256

6.10Timebase

Timebase, generated by 32kHz crystal oscillator, is a combination

of frequency selection.

Furthermore, timebase generates 4KHz,

2KHz, 512Hz, 64Hz, 16Hz and 2Hz interrupt sources for

Real-Time-Clock

6.11 Sleep Mode, Wakeup, and Watchdog

6.11.1 Sleep and wakeup modes

Sleep: After power-on reset, IC starts running until a sleep

command is issued.

When a sleep command is

accepted, IC will turn the system clock (PLL) off.

After all, it enters sleep mode.

Wakeup: CPU awaking from sleep mode requires a wakeup

signal to turn the system clock (PLL) on.

The

FIQ/IRQ signal makes CPU to complete the

wakeup process and initialization.

6.11.2 Watchdog Reset

The GPCE2P064B provides another important feature, watchdog

reset.

If the watchdog function is enabled, a reset signal is

generated to reset system when watchdog counter is overflow.

The purpose of watchdog is to monitor whether the system

operates normally.

Within a certain period, watchdog register

must be cleared.

If it is not cleared, CPU assumes the program

has been running in an abnormal condition.

As a result, the

CPU will reset the system to the initial state and start running the

program all over again.

6.12 Soft Reset Protection

Software reset.

Writing $5555 into P_System_Reset will reset

the whole system similar to hardware reset (pull low RESETB

pin), except a flag will set on in P_System_LVD_Ctrl(R/W).

6.13 ADC (Analog to Digital Converter) / DAC

The GPCE2P064B has eight channels 12-bit ADC (Analog to

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