GPCE2P064B

© Generalplus Technology Inc.

Proprietary & Confidential

6

Apr. 07, 2015

Version: 1.2

5.1.2 SOP24 (HS101) pin descriptions

Mnemonic

PIN No.

(HS101)

Type

Description

PORT A, Port B

IOA[0]

IOA[12]

IOA[13]

IOA[14]

IOA[15]

14

15

16

17

18

I/O

IOA : bi-directional I/O ports

It can be programmed as wakeup I/O pins

IOB [2]

IOB [3]

11

12

I/O

IOB : bi-directional I/O ports

Under OTP ROM programming mode, IOB2SCK, IOB3SDA.

Power & GND

VDD_IOA

19

P

Power VDD for Port A

VDD_IOB

13

P

Power VDD for Port B

V3_ADC

9

P

Power VDD for AD

VSS_ADC

8

G

Power GND for AD

V3_REGO

1

P

3V power output from regulator

VDD_REG

24

P

Positive supply for regulator(2.4V~5.5V)

VSS_REG

2

G

Ground reference for regulator

VDD_PDAC

22

P

Positive 5V supply for push-pull DAC post driver

VSS_ PDAC

20

I

Ground reference for push-pull DAC post driver

OPTION

TEST

7

I

TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull low)

VPP

3

I

High voltage during OTP programming.

NC at the normal run.

EPM

4

I

Program control input. Connect to VDDIN during OTP programming. NC at normal run

DAC

AUDP

21

O

Audio output of push pull DAC

AUDN

23

O

Audio output of push pull DAC

ADC

VADREF

10

O

AVREF_DA reference pin

PLL

VCOIN

5

I

PLL low pass filter input

Other Signal

RESETB

6

I

System reset pin (active low)