GPCE2P064B datasheet(11/25 Pages) GENERALPLUS

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GPCE2P064B

Proprietary & Confidential

Apr. 07, 2015

Version: 1.2

6 FUNCTION DESCRIPTIONS

6.1 CPU

The GPCE2P064B is equipped with a 16-bit

’nSP™, the newest

16-bit microprocessor (pronounced as micro-n-SP).

Eight

registers are involved in

’nSP™: R1 - R4 (General-purpose

registers), PC (Program Counter), SP (Stack Pointer), Base

Pointer (BP) and SR (Segment Register).

The interrupts include

three FIQs (Fast Interrupt Request) and eight IRQs (Interrupt

Request), plus one software-interrupt, BREAK.

6.2 Memory

6.2.1 SRAM

The amount of SRAM is 2K-word (including Stack), ranged from

$0000 through $07FF with access speed of two CPU clock

cycles.

6.2.2 OTP ROM

GPCE2P064B features a 32K-word high-speed OTP ROM.

6.3 PLL, Clock, Power Mode

6.3.1 PLL (Phase Lock Loop)

The purpose of PLL is to provide a base frequency (32kHz) and

to pump the frequency from 20.48MHz to 49.152MHz for system

clock (FOSC).

The default PLL frequency is 24.576MHz.

6.3.1.1

System clock

Basically, the system clock is provided by PLL and programmed

by the Port_SystemClock (R/W) to determine the clock frequency

for system.

The default system clock FOSC = 24.576MHz and

CPU clock is FOSC/8 if not specified.

The initial CPU clock is

Fosc/8 after system wakes up and adjusts to desired CPU clock

via programming the Port_SystemClock (R/W).

This avoids

ROM reading failure when system awakes.

6.3.1.2

32KHz clock

The 32KHz clock is normally used in watch, clock or other time

related products.

A 2Hz (0.5 seconds) function is loaded in

GPCE2P064B.

It counts the time as well as to wake CPU up

whenever 2Hz occurs.

Since the clock is generated each 0.5

seconds, time can be traced by the number of 32KHz

occurrences.

In addition, GPCE2P064B supports 32KHz

internal resistor oscillator in normal mode and auto-power-saving

mode.

6.4 Standby Mode

The GPCE2P064B features a power savings mode (or called

standby mode) for low power applications.

To enter standby

mode, the desired key wakeup port (IOA[15:0]) must be

configured to input first.

And read the Port_IOA_Data to latch

the IOA state before entering the standby mode.

Also

remember to enable the corresponding interrupt source(s) for

wakeup.

After that, stop the CPU clock by writing $5555 into

Port_System_Sleep(W) to enter standby mode.

In such mode,

SRAM and I/Os remain in the previous states until CPU being

awakened.

The wakeup sources in GPCE2P064B include KEY

wakeup (IOA[15:0]), 32KHz wakeup, FIQ and IRQ0 - IRQ7.

After GPCE2P064B is awakened, CPU will continue to execute

the program from where it slept.

Programmer can also enable

or disable the 32kHz when CPU is in standby mode.

6.5 Low Voltage Detection and Low Voltage Reset

6.5.1

Low voltage detection (LVD)

The Low Voltage Detection (LVD) reports the circumstance of

present voltage.

There are four LVD levels to be selected: 2.6V,

2.8V, 3.0V and 3.2V.

Those levels can be programmed via

P_LVD_Ctrl.

As an example here, suppose LVD is given 2.8V.

When the voltage drops below 2.8V, the b12 of P_LVD_Ctrl is

read as HIGH.

In such state, program can be designed to

response this condition.

6.5.2

Low voltage reset

In addition to the LVD, the GPCE2P064B has another important

function, Low Voltage Reset (LVR).

With the LVR function, a

reset signal is generated to reset system when the operating

voltage drops below LVR level.

Without LVR, the CPU becomes

unstable and malfunctions when the operating voltage drops

below LVR level.

The LVR will reset all functions to the initial

operational (stable) states when the voltage drops below LVR

level.

6.6 Interrupt

The GPCE2P064B has 13 interrupt sources, grouped into two

types, FIQ (Fast Interrupt Request) and IRQ (Interrupt request).

The priority of FIQ is higher than IRQ.

FIQ is a high-priority

interrupt while IRQ is the low-priority one.

An IRQ can be

interrupted by a FIQ, but not by another IRQ.

A FIQ cannot be

interrupted by any other interrupt sources.

6.7 I/O

Two I/O ports are built in GPCE2P064B - PortA and PortB, total

has 20 bit-programmable I/Os.

The PortA is a general purpose

I/O with programmable wakeup capability, i.e. IOA [15:0] is the

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