GPCE2P064B

© Generalplus Technology Inc.

Proprietary & Confidential

5

Apr. 07, 2015

Version: 1.2

5 SIGNAL DESCRIPTIONS

5.1 Signal Pin

5.1.1 All Pins and LQFP64 pin descriptions

Mnemonic

PIN No.

(LQFP64)

Type

Description

PORT A, Port B

IOA[15:0]

37-30,27-20

I/O

IOA[15:0]: bi-directional I/O ports

It can be programmed as wakeup I/O pins

IOB [3:0]

18-15

I/O

IOB [3:0]: bi-directional I/O ports

Under OTP ROM programming mode, IOB2SCK, IOB3SDA.

Power & GND

VDD_IOA

29

P

Power VDD for Port A

VSS_IO

28

G

Power GND for IO Port

VDD_IOB

19

P

Power VDD for Port B

V3_ADC

7

P

Power VDD for AD

VSS_ADC

6

G

Power GND for AD

V3_REGO

63

P

3V power output from regulator

VDD_REG

62

P

Positive supply for regulator(2.4V~5.5V)

VSS_REG

64

G

Ground reference for regulator

VDD_DAC

54

P

Positive 5V supply for push-pull DAC

VDD_PDAC

50

P

Positive 5V supply for push-pull DAC post driver

VSS_DAC

53

I

Ground reference for push-pull DAC

VSS_ PDAC

48,52

I

Ground reference for push-pull DAC post driver

OPTION

TEST

5

I

TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull low)

VPP

1

I

High voltage during OTP programming.

NC at the normal run.

EPM

2

I

Program control input. Connect to VDDIN during OTP programming. NC at normal run

DAC

AUDP

49

O

Audio output of push pull DAC

AUDN

51

O

Audio output of push pull DAC

ACIN

55

U

Audio analog mixer in

ADC

MICP

14

I

MIC amplifier input positive (Internal Floating)

MICN

13

I

MIC amplifier input negative (refer to application circuit)

MICOUT

12

O

MIC amplifier output (refer to application circuit)

OPI

11

I

Audio amplifier negative input (refer to application circuit)

AGC

10

IO

AGC by pass filter (refer to application circuit)

VMIC

8

O

Microphone power supply

VADREF

9

O

AVREF_DA reference pin

PLL

VCOIN

3

I

PLL low pass filter input

Other Signal

RESETB

4

I

System reset pin (active low)