NT5CB128M16IP-EKB datasheet(96/162 Pages) NANYA

96 / 162 page

Version 2.1

Nanya Technology Cooperation ©

07/2017

NTC Proprietary

Level: Property

DDR3(L) 2Gb SDRAM

NT5CB(C)256M8IN / NT5CB(C)128M16IP

DDR3 Differential AC and DC Input Levels for clock (CK - ) and strobe (DQS - )

Symbol

Parameter

DDR3-800, 1066, 1333, & 1600

Unit

Notes

Min

Max

VIHdiff

Differential input high

+ 0.200

Note 3

VILdiff

Differential input logic low

Note 3

- 0.200

VIHdiff(ac)

Differential input high ac

2 x (VIH(ac) - Vref)

Note 3

VILdiff(ac)

Differential input low ac

Note 3

2 x (VIL(ac) - Vref)

NOTE 1. Used to define a differential signal slew-rate.

NOTE 2. For CK -

 use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - , DQSL, L, DQSU ,U use VIH/VIL(ac) of

DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,then the reduced level applies also here.

NOTE 3. These values are not defined; however, the single-ended signals CK,

, DQS, , DQSL, L, DQSU,

U need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for

overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications”

DDR3L Differential AC and DC Input Levels for clock (CK - ) and strobe (DQS - )

Symbol

Parameter

DDR3L-1066, 1333, 1600 & 1866

Unit

Notes

Min

Max

VIHdiff

Differential input high

+ 0.180

Note 3

VILdiff

Differential input logic low

Note 3

- 0.180

VIHdiff(ac)

Differential input high ac

2 x (VIH(ac) - Vref)

Note 3

VILdiff(ac)

Differential input low ac

Note 3

2 x (VIL(ac) - Vref)

NOTE 1 Used to define a differential signal slew-rate.

NOTE 2 For CK -

 use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - , DQSL, L, DQSU , U use VIH/VIL(AC) of

DQs and VREFDQ; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.

NOTE 3 These values are not defined, however the single-ended signals CK,

, DQS, , DQSL, L, DQSU, U need to be

within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and

undershoot. Refer to “Overshoot and Undershoot Specifications”.

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