NT5CB128M16IP-EKB datasheet(32/162 Pages) NANYA

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Version 2.1

Nanya Technology Cooperation ©

07/2017

NTC Proprietary

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DDR3(L) 2Gb SDRAM

NT5CB(C)256M8IN / NT5CB(C)128M16IP

DDR3(L) SDRAM Command Description and Operation

Command Truth Table (Conti.)

NOTE1. All DDR3(L) SDRAM commands are defined by states of

, RA, A, WEand CKE at the rising edge of the clock. The MSB of

BA, RA and CA are device density and configuration dependant.

NOTE2.

REET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function.

NOTE3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.

NOTE4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.

NOTE5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.

NOTE6. The Power-Down Mode does not perform any refresh operation.

NOTE7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

NOTE8. Self Refresh Exit is asynchronous.

NOTE9. VREF (Both VrefDQ and VrefCA) must be maintained during Self Refresh operation.

NOTE10. The No Operation command should be used in cases when the DDR3(L) SDRAM is in an idle or wait state. The purpose of the

No Operation command (NOP) is to prevent the DDR3(L) SDRAM from registering any unwanted commands between operations.

A No Operation command will not terminate a pervious operation that is still executing, such as a burst read or write cycle.

NOTE11. The Deselect command performs the same function as No Operation command.

NOTE12. Refer to the CKE Truth Table for more detail with CKE transition.

NT5CB128M16IP-EKB 数据表(PDF) 32 Page - Nanya Technology Corporation.