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NT5CB128M16IP-EKB 数据表(PDF) 48 Page - Nanya Technology Corporation. |
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NT5CB128M16IP-EKB 数据表(HTML) 48 Page - Nanya Technology Corporation. |
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48 / 162 page  Version 2.1 48 Nanya Technology Cooperation © 07/2017 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 2Gb SDRAM NT5CB(C)256M8IN / NT5CB(C)128M16IP MPR Register Address Definition The following table provide an overview of the available data location, how they are addressed by MR3 A[1:0] during a MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read. MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] Function Burst Length Read Address A[2:0] Burst Order and Data Pattern 1 00 Read Predefined Pattern for System Calibration BL8 000 Burst order 0,1,2,3,4,5,6,7 Pre-defined Data Pattern [0,1,0,1,0,1,0,1] BC4 000 Burst order 0,1,2,3 Pre-defined Data Pattern [0,1,0,1] BC4 100 Burst order 4,5,6,7 Pre-defined Data Pattern [0,1,0,1] 1 01 RFU BL8 000 Burst order 0,1,2,3,4,5,6,7 BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 1 10 RFU BL8 000 Burst order 0,1,2,3,4,5,6,7 BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 1 11 RFU BL8 000 Burst order 0,1,2,3,4,5,6,7 BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 Note: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent. ACTIVE Command The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The value on the BA0-BA2 inputs selects the bank, and the addresses provided on inputs A0-A15 selects the row. These rows remain active (or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. |
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