NT5CB128M16IP-EKB datasheet(3/162 Pages) NANYA

部件名	NT5CB128M16IP-EKB

功能描述	Commercial, Industrial and Automotive DDR3(L) 2Gb SDRAM

PDF	162 Pages

Scroll/Zoom	100%

制造商	NANYA [Nanya Technology Corporation.]

网页	http://www.nanya.com

标志

3 / 162 page

Version 2.1

Nanya Technology Cooperation ©

07/2017

NTC Proprietary

Level: Property

DDR3(L) 2Gb SDRAM

NT5CB(C)256M8IN / NT5CB(C)128M16IP

Descriptions

The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation. It is

internally configured as an eight bank DRAMs.

The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices. These

synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general

applications.

The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address

inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross

point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or

differential DQS pair in a source synchronous fashion.

These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in

BGA packages.

NT5CB128M16IP-EKB 数据表(PDF) 3 Page - Nanya Technology Corporation.