GD25B127DFES datasheet(18/65 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B127D

7.5. Write Status Register (WRSR) (01H or 31H or 11H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be

accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)

command has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) command has no effect on S20, S19, S17, S16, S15, S10, S1 and S0 of the Status

Register. CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register

(WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose

duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check

the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register

cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,

BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register (WRSR)

command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits.

Figure7. Write Status Register Sequence Diagram

7.6. Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the

rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit is shifted out, at a Max

frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically

incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read

with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or

Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure8. Read Data Bytes Sequence Diagram

Command

01H/31H/11H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Status Register in

Command

03H

CS#

SCLK

High-Z

9 10

28 29 30 31 32

MSB

34 35 36 37

23 22 21

38 39

24-bit address

MSB

Data Out1

Data Out2

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