GD25B127DFES datasheet(12/65 Pages) GIGADEVICE

12 / 65 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B127D

LB3, LB2, LB1 bits.

The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the

write protect control and status to the Security Registers. The default state of LB3-LB1are 0, the security registers are

unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time

Programmable, once they are set to 1, the Security Registers will become read-only permanently.

CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction with the BP4-BP0

bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details.

The default setting is CMP=0.

SUS1, SUS2 bits

The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an

Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the

SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command, software reset

(66H+99H) command as well as a power-down, power-up cycle.

DRV1, DRV0 bits

The DRV1&DRV0 bits are used to determine the output driver strength for the Read operations.

DRV1, DRV0

Driver Strength

100%

75%

50% (default)

25%

GD25B127DFES 数据表(PDF) 12 Page - GigaDevice Semiconductor (Beijing) Inc.