GD25WD80C datasheet(9/47 Pages) GIGADEVICE

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Uniform Sector

Standard and Dual Serial Flash

GD25WD80C

5. DATA PROTECTION

The GD25WD80C provides the following data protection methods:

◆

Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will

reset to 0 in the following situations:

-Power-Up

-Write Disable (WRDI)

-Write Status Register (WRSR)

-Page Program (PP)

-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)

◆

Software Protection Mode: The Block Protect (BP2, BP1, BP0) bits define the section of the protected memory area

which is read-only and unalterable.

◆

Hardware Protection Mode: WP# goes low to protect the BP0~BP2 bits and SRP bits.

◆

Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep

Power-Down Mode command.

◆

Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI.

Table1. GD25WD80C Protected area size

Status Register Content

Memory Content

BP2

BP1

BP0

Blocks

Addresses

Density

Portion

NONE

Sector 0 to 253

000000H-0FDFFFH

1016KB

Lower 254/256

Sector 0 to 251

000000H-0FBFFFH

1008KB

Lower 252/256

Sector 0 to 247

000000H-0F7FFFH

992KB

Lower 248/256

Sector 0 to 239

000000H-0EFFFFH

960KB

Lower 240/256

Sector 0 to 223

000000H-0DFFFFH

896KB

Lower 224/256

Sector 0 to 191

000000H-0BFFFFH

768KB

Lower 192/256

All

000000H-0FFFFFH

1024KB

ALL

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