GD25VQ127CSFS datasheet(18/62 Pages) GIGADEVICE

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Uniform Sector

Dual and Quad Serial Flash

GD25VQ127C

Figure5. Write Enable for Volatile Status Register Sequence Diagram

7.4. Read Status Register (RDSR) (05H or 35H or 15H)

The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at

any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress,

it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is also possible

to read the Status Register continuously.

For command code “05H”/ “35H” / “15H”, the SO will output Status Register bits

S7~S0/ S15-S8 / S23-S16.

Figure6. Read Status Register Sequence Diagram

7.5. Write Status Register (WRSR) (01H or 31H or 11H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be

accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)

command has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) command has no effect on S20, S19, S17, S16, S15, S10, S1 and S0 of the Status

Register. CS# must be driven high after the eighth of the data byte has been latched in. If not, the Write Status Register

(WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose

duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check

the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register

cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,

BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only. The Write Status Register (WRSR)

command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the

Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (WP#) signal allow the

device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the

CS#

SCLK

Command(50H)

High-Z

Command

05H or 35H or 15H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Register0/1/2

MSB

Register0/1/2

GD25VQ127CSFS 数据表(PDF) 18 Page - GigaDevice Semiconductor (Beijing) Inc.

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