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GD25VQ127CSFS 数据表(PDF) 22 Page - GigaDevice Semiconductor (Beijing) Inc.

部件名 GD25VQ127CSFS
功能描述  Uniform Sector Dual and Quad Serial Flash
PDF  62 Pages
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制造商  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
网页  http://www.gigadevice.com/
标志 GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25VQ127CSFS 数据表(HTML) 22 Page - GigaDevice Semiconductor (Beijing) Inc.

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Uniform Sector
Dual and Quad Serial Flash
GD25VQ127C
22
Figure12. Dual I/O Fast Read Sequence Diagram (M5-4
≠(1, 0))
Figure12a. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))
7.11.
Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-byte address (A23-
0) and a “Continuous Read Mode” byte and 4-dummy clock4-bit per clock by IO0, IO1, IO2, IO3, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure13. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit
(QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command.
Command
0
1
2
3
4
5
6
7
BBH
CS#
SCLK
SI(IO0)
SO(IO1)
8
9 10 11 12 13 14 15
6
4
2
0
6
4
2
0
16 17 18 19 20 21 22 23
6
4
2
0
6
4
7
5
3
1
7
5
3
1
7
5
3
1
7
5
A23-16
A15-8
A7-0
M7-4
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SI(IO0)
SO(IO1)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
SCLK
6
7
Byte1
Byte2
Byte3
Byte4
Dummy
0
1
2
3
4
5
6
7
CS#
SCLK
8
9 10 11 12 13 14 15
6
4
2
0
6
4
2
0
6
4
2
0
6
4
7
5
3
1
7
5
3
1
7
5
3
1
7
5
A23-16
A15-8
A7-0
M7-4
CS#
23 24 25 26 27 28 29 30 31
SI(IO0)
SO(IO1)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
SCLK
6
7
Byte1
Byte2
Byte3
Byte4
15 16 17 18 19 20 21 22
Dummy



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