ADPA7002CHIP

Data Sheet

Rev. 0 | Page 18 of 23

BIASING PROCEDURES

The ADPA7002CHIP is a GaAs, pHEMT, MMIC power amplifier.

Figure 54). The internal connections of the bypass capacitors are

shown in Figure 56.

All measurements for this device are taken using the typical

application circuit (see Figure 54) and configured as shown in the

assembly diagram (see Figure 53).

Adhere to the following bias sequence during power-up:

1.

Connect GND to RF and dc ground.

2.

3.

4.

Increase the gate bias voltage to achieve a quiescent current,

5.

Apply the RF signal.

Adhere to the following bias sequence during power-down:

1.

Turn off the RF signal.

2.

3.

Decrease all drain bias voltages to 0 V.

4.

Decrease the gate bias voltage to 0 V.

Simplified bias pad connections to dedicated gain stages, as well as

dependence and independence among pads are shown in

Figure 54.

(mA)

Gain

(dB)

P1dB

(dBm)

Output IP3

(dBm)

(W)

600

17.2

30.04

40.6

3

−0.73

700

17.7

30.24

38.7

3.5

−0.67

800

18.0

30.25

37.0

4

−0.62

to optimize overall performance. Unless otherwise noted, the data

shown in the Typical Performance Characteristics section is

taken using the recommended bias conditions. Operating the

ADPA7002CHIP at different bias conditions can provide

performance that differs from what is shown in Table 1 and Table 2.

Biasing the ADPA7002CHIP for higher drain current typically

results in higher P1dB, output IP3, and signal gain at the expense of

increased power consumption (see Table 5 for bias selection per

performance).

BIASING THE ADPA7002CHIP WITH THE

HMC980LP4E

The HMC980LP4E is an active bias controller that is designed to

meet the bias requirement for enhancement mode and depletion

mode amplifiers like the ADPA7002CHIP. The HMC980LP4E

provides constant current biasing over temperature and device to

device variation. Additionally, the HMC980LP4E properly

sequences gate and drain voltages to ensure safe amplifier

operation, and offers self protection in the event of a short circuit.

The active bias controller contains an internal charge pump that

generates negative voltage that is needed for the ADPA7002CHIP

gate and that can also be used as an external negative voltage

source.

For more information regarding the usage of HMC980LP4E, refer

to the HMC980LP4E data sheet and the AN-1363 application note.

Figure 58. Functional Diagram of HMC980LP4E

Application Circuit Setup

Figure 59 shows a schematic of an application circuit of the

HMC980LP4E used with the ADPA7002CHIP. Refer to Figure 60

for an application circuit diagram if using external negative supply

for the VNEG pin.

In the application circuit, the ADPA7002CHIP drain voltage and

drain current are set by the following equations:

IDRAIN = 150 Ω × R10 (187 Ω)

where:

IDRAIN is the output current from Pin 17 and Pin 18 on the

HMC980LP4E.

Requirement

When using the ADPA7002CHIP with the HMC980LP4E, the

minimum voltages for VNEG and VGATE need to be limited to

−1.5 V to keep them within the absolute maximum ratings (AMR)

setting the R15 resistor and the R16 resistor to the values shown in

Figure 59 and Figure 60. Refer to the AN-1363 application note for

more information and calculations for R15 and R16.

VDD

VDD

S0

S1

EN

ALM

VDRAIN

VDRAIN

VGATE

GATE

CONTROL

VNEG

VG2

VG2_CONT

PACKAGE

BASE

HMC980LP4E

CONTROL

BLOCK

BAND GAP

NEGATIVE

VOLTAGE

GENERATOR

GND

1

2

3

4

5

6

18

17

16

15

14

13

7

8

9

10

11

12

23

22

21

20

19

24