ADPA7002CHIP

Data Sheet

Rev. 0 | Page 20 of 23

HMC980LP4E Bias Sequence

Proper dc supply sequencing is required to prevent damage to

HMC980LP4E. Adhere to the following power-up sequence steps:

1. Set VDIG, the voltage supply input (Pin 9) for the

HMC980LP4E digital circuit (see Figure 60) to 3.3 V.

2. Set S0, the digital control pin (Pin 3) that sets the internal

field effect transistor (FET) and the internal HMC980LP4E

resistor (RDS) resistance (see Figure 60) to 3.3 V.

4. Set VNEG to −1.5 V. This step is not needed if using

internally generated voltage.

5. Set the EN pad to 3.3 V. Transitioning from 0 V to 3.3 V

turns on the VGATE and VDRAIN pads.

Adhere to the following power-down sequence steps:

1. Set the EN pad to 0 V. Transitioning from 3.3 V to 0 V

turns off the VDRAIN and VGATE pads.

2. Set VNEG to 0 V. This step is not required if using

internally generated voltage.

4. Set S0 to 0 V.

5. Set VDIG to 0 V.

When the HMC980LP4E bias control circuit has been set up, the

ADPA7002CHIP bias can be toggled on and off by applying 3.3 V

or 0 V to the EN pad. If EN is set to +3.3 V, VGATE drops to

−1.5 V and VDRAIN is turned on at +5 V. VGATE rises in voltage

until IDRAIN equals 800 mA. The closed control loop then

regulates IDRAIN at 800 mA. When the EN pad equals 0 V,

VGATE is automatically set to −1.5 V and VDRAIN is set to 0 V

(see Figure 61 and Figure 62).

Figure 61. Turn On—HMC980LP4E Outputs to the ADPA7002CHIP

Figure 62. Turn Off—HMC980LP4E Outputs to the ADPA7002CHIP

Constant Drain Current Biasing vs. Constant Gate

Voltage Biasing

The HMC980LP4E uses closed loop feedback to continuously

adjust VGATE to maintain a constant gate current bias over dc

supply variation, temperature and part to part variation. Constant

drain current bias is an excellent method for reducing time in

calibration procedures and to maintain consistent performance

over time.

In comparison to a constant gate voltage bias, where the current

increases when RF power is applied, a constant drain current

has a slightly lower output P1dB. This effect can be seen in

Figure 64 and Figure 66, where RF performance is slightly lower

than constant gate voltage bias operation. RF performance is

lower due to a lower drain current at high input power levels as

the HMC980LP4E reaches 1 dB compression.

The output P1dB performance for the constant drain current

bias improves if the constant gate voltage bias is increased. By

to the RF drive in the constant gate voltage bias condition shown in

Figure 64.

current operation is usually set by the thermal limitations found

in the table from the Absolute Maximum Ratings section along

with the maximum power dissipation specification. Increasing

and the power dissipation increases. Therefore, consider the trade-

off between power dissipation and output P1dB performance when

using constant drain current biasing.

CH2 1.00V

CH3 2.00V

CH4 2.00V

M20.0ms

A CH1

1.12V

3

1

VDD

VDRAIN

EN

VGATE

CH2 1.00V

CH3 2.00V

CH4 2.00V

M20.0ms

A CH1

1.12V

3

1

VDD

VDRAIN

EN

VGATE