 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TUSB8043AI 数据表(PDF) 41 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TUSB8043AI 数据表(HTML) 41 Page - Texas Instruments |
|
|
41 / 56 page  USB_SSTXP_UP USB_SSTXM_UP VBUS CAP_UP_TXM CAP_UP_TXP USB_SSRXP_UP USB_SSRXM_UP USB_DP_UP USB_DM_UP TUSB8043A U1A USB_VBUS 48 USB_DP_UP 53 USB_DM_UP 54 USB_SSTXP_UP 55 USB_SSTXM_UP 56 USB_SSRXP_UP 58 USB_SSRXM_UP 59 FULLPWRMGMTZ/SMBA1/SS_UP 40 GANGED/SMBA2/HS_UP 42 C1 10uF C3 0.1uF 0201 C4 0.1uF R3 4.7K 0402 5% J1 USB3_TYPEB_CONNECTOR VBUS 1 DM 2 DP 3 GND 4 SSTXN 5 SSTXP 6 GND 7 SSRXN 8 SSRXP 9 SHIELD0 10 SHIELD1 11 R5 1M 0402 5% R4 4.7K 0402 5% C5 0.001uF R2 10K 1% 0402 1% R1 90.9K 0402 1% C2 0.1uF 0201 41 TUSB8043A www.ti.com SLLSF94 – JUNE 2019 Product Folder Links: TUSB8043A Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Typical Application (continued) 9.2.1.1 Design Requirements Table 31. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VDD Supply 1.1 V VDD33 Supply 3.3 V Upstream Port USB Support (SS, HS, FS) SS, HS, FS Downstream Port 1 USB Support (SS, HS, FS, LS) SS, HS, FS, LS Downstream Port 2 USB Support (SS, HS, FS, LS) SS, HS, FS, LS Downstream Port 3 USB Support (SS, HS, FS, LS) SS, HS, FS, LS Downstream Port 4 USB Support (SS, HS, FS, LS) SS, HS, FS, LS Number of Removable external exposed Downstream Ports 4 Number of Non-Removable external exposed Downstream Ports 0 Full Power Management of Downstream Ports Yes. (FULLPWRMGMTZ = 0) Individual Control of Downstream Port Power Switch Yes. (GANGED = 0) Power Switch Enable Polarity Active High. (PWRCTL_POL = 1) Battery Charge Support for Downstream Port 1 Yes Battery Charge Support for Downstream Port 2 Yes Battery Charge Support for Downstream Port 3 Yes Battery Charge Support for Downstream Port 4 Yes I2C EEPROM Support No 24MHz Clock Source Crystal 9.2.1.2 Detailed Design Procedure 9.2.1.2.1 Upstream Port Implementation The upstream of the TUSB8043A is connected to a USB3 Type B connector. This particular example has GANGED pin and FULLPWRMGMTZ pin pulled low which results in individual power support each downstream port. The VBUS signal from the USB3 Type B connector is feed through a voltage divider. The purpose of the voltage divider is to make sure the level meets USB_VBUS input requirements Figure 28. Upstream Port Implementation |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
