TUSB8043AI datasheet(50/56 Pages) TI1

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TUSB8043A

SLLSF94 – JUNE 2019

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11 Layout

11.1 Layout Guidelines

11.1.1 Placement

1. 9.53K +/-1% resistor connected to pin USB_R1 should be placed as close as possible to the TUSB8043A.

2. A 0.1 µF should be placed as close as possible on each VDD and VDD33 power pin.

3. The 100 nF capacitors on the SSTXP and SSTXM nets should be placed close to the USB connector (Type

A, Type B, and so forth).

4. The ESD and EMI protection devices (if used) should also be placed as close as possible to the USB

connector.

5. If a crystal is used, it must be placed as close as possible to the TUSB8043A XI and XO pins.

6. Place voltage regulators as far away as possible from the TUSB8043A, the crystal, and the differential pairs.

7. In general, the large bulk capacitors associated with each power rail should be placed as close as possible to

the voltage regulators.

11.1.2 Package Specific

1. The TUSB8043A package has a 0.5-mm pin pitch.

2. The TUSB8043A package has a 6.0-mm x 6.0-mm thermal pad. This thermal pad must be connected to

ground through a system of vias.

3. All vias under device, except for those connected to thermal pad, should be solder masked to avoid any

potential issues with thermal pad layouts.

11.1.3 Differential Pairs

This section describes the layout recommendations for all the TUSB8043A differential pairs: USB_DP_XX,

USB_DM_XX, USB_SSTXP_XX, USB_SSTXM_XX, USB_SSRXP_XX, and USB_SSRXM_XX.

1. Must be designed with a differential impedance of 90 Ω ±10%.

2. In order to minimize cross talk, it is recommended to keep high speed signals away from each other. Each

pair should be separated by at least 5 times the signal trace width. Separating with ground as depicted in the

layout example also helps minimize cross talk.

3. Route all differential pairs on the same layer adjacent to a solid ground plane.

4. Do not route differential pairs over any plane split.

5. Adding test points causes impedance discontinuity; and therefore, negative impacts signal performance. If

test points are used, they should be placed in series and symmetrically. They must not be placed in a

manner that causes stub on the differential pair.

6. Avoid 90 degree turns in trace. The use of bends in differential traces should be kept to a minimum. When

bends are used, the number of left and right bends should be as equal as possible and the angle of the bend

should be

≥ 135 degrees. This minimizes any length mismatch causes by the bends and therefore minimize

the impact bends have on EMI.

7. Minimize the trace lengths of the differential pair traces. The maximum recommended trace length for SS

differential pair signals and USB 2.0 differential pair signals is eight inches. Longer trace lengths require very

careful routing to assure proper signal integrity.

8. Match the etch lengths of the differential pair traces (i.e. DP and DM or SSRXP and SSRXM or SSTXP and

SSTXM). There should be less than 5 mils difference between a SS differential pair signal and its

complement. The USB 2.0 differential pairs should not exceed 50 mils relative trace length difference.

9. The etch lengths of the differential pair groups do not need to match (i.e. the length of the SSRX pair to that

of the SSTX pair), but all trace lengths should be minimized.

10. Minimize the use of vias in the differential pair paths as much as possible. If this is not practical, make sure

that the same via type and placement are used for both signals in a pair. Any vias used should be placed as

close as possible to the TUSB8043A device.

11. To ease routing, the polarity of the SS differential pairs can be swapped. This means that SSTXP can be

routed to SSTXM or SSRXM can be routed to SSRXP.

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