STLC1510 datasheet(13/40 Pages) STMICROELECTRONICS

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STLC1510

n=< 4 at ATM layers intended for 622 Mbps.

This interface is subdivided into two parts: the

Transmit Interface (TxIF) and the Receive

Interface (RxIF).

Both the TxIF and RxIF are controlled by the

ATM layer.

The ATM layer provides an interface clock to the

PHY layer for synchronizing all interface

transfers.

The PHY layer will incorporate rate-matching

buffers.

Transmit data is transferred from the ATM layer

to the PHY layer as follows: first, the PHY layer

indicates it can accept data, then the ATM layer

drives data onto the data bus and asserts the

TxEnb.

The data flow is controlled by the PHY layer.

For a complete definition of TxIF signals and RxIF

signals please consult the UTOPIA Level 1 and UTO-

PIA Level 2 documents released by The ATM Forum

Technical Committee.

There is an additional signal added to the Utopia In-

terface in the TX direction: Back Pressure (TxBP).

This signal alerts the backplane when a software pro-

grammable depth has been reached in the TX Utopia

FIFO, while still allowing more data (up to the 10 cells

maximum) to be accepted by the FIFO.

5.1.5 ATM Transport Convergence (TC) Layer

Processor

The Cell TC block has the following attributes:

Idle cells inserted in the Tx direction for cell rate

de-coupling are discarded.

HEC bytes are generated in the Tx direction as

described in ITU-T Recommendation I.432,

including the recommended modulo-2 addition

(XOR) of the pattern binary 01010101 to the

HEC bits.

Scrambling of the cell payload is used in the

transmit direction to improve the security and

robustness of the HEC cell delineation

mechanism. The cell payload is descrambled by

the Cell TC block of an ATU receiver.

When interfacing ATM bytes to the bearer

channel, the most significant bit (msb) is sent

first.

Cell delineation is performed using a coding law

checking the HEC field in the cell header

according to the algorithm described in ITU-T

Recommendation I.432.

Error detection is performed as defined in ITU-T

Recommendation I.432 with the exception that

any HEC error is considered a multiple-bit error.

Therefore, HEC error correction is not

performed.

The ATU-C transmitter preserves V-C and T-R

interface byte boundaries (explicitly present or

implied by ATM cell boundaries) at the U-C

interface.

Interfaces to the Lamba bus.

5.2 FIFO

The STLC1510 incorporates 4 FIFO buffers for rate

decoupling:

Utopia TX FIFO (8 bit input from the Utopia TX

interface, 16 bit output to the ATM-TC cell

processor): 243 words X 16 bits/word = 486

bytes >= 9 ATM cells @ 53 bytes/cell

Utopia RX FIFO (16 bit input from the ATM-TC

cell processor, 8 bit output to the Utopia RX

interface): 54 words X 16 bits/word = 108 bytes

>= 2 ATM cells @ 53 bytes/cell

Lamba TX FIFO (16 bit input from the ATM-TC

cell processor, 8 bit output to the Lamba Bus):

106 words X 16 bits/word = 212 bytes >= 4 ATM

cells @ 53 bytes/cell

Lamba RX FIFO (8 bit input from the Lamba

Bus, 16 bit output to the ATM-TC cell

processor): 106 words X 16 bits/word = 212

bytes >= 4 ATM cells @ 53 bytes/cell

All the FIFO’s share the following features:

Perform 8-bit to 16-bit word conversion or 16-bit

to 8-bit word conversion, with storage

implemented as 16-bit wide dual port RAMs.

Flags indicating when the FIFO is full, almost

full, empty, almost empty and half empty. (The

FIFO depths for the almost full and almost

empty flags are hard-wired).

Diagnostic input and an error flag.

The Utopia Tx FIFO has the following additional

attributes:

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