STLC1510 datasheet(21/40 Pages) STMICROELECTRONICS

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STLC1510

5.10 Timing Generation Block (TGB)

The timing and reset generation block generates the

device’s global clock and synchronization

signals.

It uses the input clock signal (35.328 or 17.664 MHz)

to derive the main internal clock signals, as well as all

synchronization pulses required to coordinate timing

between the sub-blocks. It also synchronizes the ex-

ternal RESETN with the internal ASIC clock.

The PLL input source, and PLL bypass signals are de-

coded from the PMode[1:0] pins. The CMode[1:0] pins

are configured to always provide an 8.8 MHz input to the

PLL when the PLL is not in bypass mode. Thus a divide

by 2 or 4 will be selected to divide down the 17 or 35

MHz input clock references to 8.8 MHz. When the PLL

is to be bypassed, it is powered down, and the input ref-

erence is used to bypass the PLL output.

The CK35M signals are generated by dividing down

the internal ASIC clock. A 3 bit memory mapped reg-

ister is used to adjust the reset phase of the divide by

6 generator. This gives software control of the phase

of the CK35M signal which interfaces to the AFE de-

vice. There is also a programmable ”one shot” mode

which is used to reset the phase of the CK35M in the

event the interface cannot synchronously meet the

timing requirements.

The NIFTX_CLK and NIFRX_CLK are generated

when the NIF is in clock and data mode, i.e. not uto-

pia mode.

5.10.1RESET Structure

The RESET structure for the STLC1510 has the fol-

lowing requirements/attributes:

Requires off-chip power supervisor to supply

10ms power-on reset (may also require push

button reset for test) and 5ms TRSTN (TAP

reset).

Reset initialization will begin when RESETN is

de-asserted by the off-chip power supervisor.

After 2 rising edges of 4.4MHz clock,

ASIC_RESETn is de-asserted and the

STLC1510 (minus the BPU and D950 cores) will

come out of reset. The ARM7 will follow its boot

procedure which at some point, will download

program code to the BPU and D950 cores then

release them individually from reset.

5.11 Test Access Port Functional Description

The IEEE 1149.1 compliant Test Access Port (TAP)

serves three purposes:

TAP interface for both ASIC and board level

testing

RAMBIST interface for testing the embedded

memories during ASIC level test.

General Purpose I/O port for general and

miscellaneous control and monitoring.

In addition to these functions, there are two sets of

mode pins, PMODE[1:0], and CMODE[1:0] which

are used to put the STLC1510 into various modes.

The definition of these modes are given below, where

the shaded rows indicate special modes not to be

used in normal operations.

Table 5. Power Mode Pin Definition

PMODE[1:0]

Mode State

Description

Power Down Mode 0

Nothing is powered down.

Power Down Mode 1

ARM7 is powered down.

Power Down Mode 2

D950 is powered down.

Power Down Mode 3

BPU processor is powered down

Table 6. Clock Mode Pin Definition

CMODE[1:0]

Mode State

Description

Div2

Master clock is REFCLK divided by 2 and then multiplied by 24. The

input REFCLK should be 17.664 MHz

Normal

Master clock is REFCLK divided by 4 and then multiplied by 24. The

input REFCLK should be 35.328 MHz

Bypass

Master clock is REFCLK

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