STLC1510 datasheet(2/40 Pages) STMICROELECTRONICS

2 / 40 page

STLC1510

2/40

2.0 LIST OF MAIN BLOCKS

The STLC1510 G.lite DMT Transceiver is formed by

the following blocks (refer to Figure 1.):

Embedded Processor Module (EPM)

The EPM includes two embedded processor cores:

the ARM7TDMI, a RISC microprocessor, and the

D950, a 16-bit DSP processor. The RISC micropro-

cessor handles the chip control, G.Lite start-up and

showtime control and DSP initialization. It also imple-

ments the Framing and Interleaving/Deinterleaving

function required by G.992.2 standard.

Block Processing Unit (BPU)

Computationally intensive digital signal processing

functions are performed in this engine. This engine

utilizes customized DSP architecture that includes

two multiplier/accumulator (MAC).

Digital Front-End (DFE)

This block provides the interface to an external ana-

log front-end (AFE) device. This block provides deci-

mation, interpolation for the signal sample for the

ADC and DAC on the AFE and signal level monitor-

ing for the analog AGC.

Network Interface (NIF)

The NIF is a selectable interface that carries the ATM

signals to and from the STLC1510. This interface

supports one parallel interface (Utopia Level 2) or a

serial data interface. The NIF includes a FIFO to buff-

er the data between the clock domains of the back-

end interface and the internal clock.

Forward Error-Correction (FEC)

The Forward Error Correction is done using Reed-

Solomon Coding. The R-S FEC encoding is per-

formed byte-wise in the transceiver on the transmit-

ted bytes. The two basic parameters that determine

the performance of the code are the code word size,

which consists of one or more DMT symbols (S), and

the number of redundant check bytes R.

Mapper/De-mapper Block (MAP)

The Mapper/De-mapper Block (MAP) performs the

bit packing and un-packing and constellation encod-

er/decoder for a G.992.2 DSL modem. This block

also supports generation of Reverb and medley.

Timing Generation Block (TGB)

The timing generation block generates global clock

and synchronization signals for the STLC1510. It

uses the input clock signals to derive the main inter-

nal and output clock signals, as well as all synchroni-

zation pulses required to coordinate timing between

the sub-blocks.

Test Access Port (TAP)

This block provides the test access to the STLC1510

using JTAG and BIST techniques.

HPI Interface

A host processor interface is provided to allow the

STLC1510 to be optionally controlled by an external

microcontroller.

3.0 TRANSIENT ENERGY CAPABILITIES

3.1 ESD

ESD (Electronic Discharged) tests have been per-

formed for the Human Body Model (HBM).

The pins of the device are to be able to withstand

minimum 2000V for the HBM.

3.2 Latch-up

The maximum sink or source current from any pin is

limited to 200mA to prevent latch-up.

4.0 ABSOLUTE MAXIMUM RATINGS

The absolute maximum ratings, as specified below,

are those ratings beyond which the device’s lifetime

may be impaired. The meeting of electrical specifica-

tions is not implied when the device is subjected to

the absolute limits.

The following table identifies the device’s minimum

and maximum ratings and along with the operating-

conditions they define the limits for testing the device

STLC1510 数据表(PDF) 2 Page - STMicroelectronics

STLC1510 数据表(HTML) 2 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载