CS8421 datasheet(8/36 Pages) CIRRUS

8 / 36 page

CS8421

DS641PP1

SWITCHING SPECIFICATIONS

(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)

Parameters

Symbol

Min

Max

Units

RST pin Low Pulse Width

(Note 6)

XTI Frequency (Note 7)

Crystal

Digital Clock Source

16.384

1.024

27.000

MHz

XTI Pulse Width High/Low

14.8

MCLK_OUT Duty Cycle

Slave Mode

I/OSCLK Frequency

24.576

MHz

OLRCK High Time

(Note 8)

tlrckh

326

I/OSCLK High Time

tsckh

I/OSCLK Low Time

tsckl

I/OLRCK Edge to I/OSCLK Rising

tlcks

OLRCK Rising Edge to OSCLK Rising Edge (TDM)

tfss

I/OSCLK Rising Edge to I/OLRCK Edge

tlckd

OSCLK Rising Edge to OLRCK Falling Edge (TDM)

tfsh

OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid

tdpd

-18

SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge

tds

SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge

tdh

OLRCK

(input)

sckh

sckl

fsh

fss

OSCLK

(input)

TDM_IN

(input)

SDOUT

(output)

MSB

dpd

MSB-1

MSB

MSB-1

lrckh

MSB

dpd

MSB-1

I/OLRCK

(input)

I/OSCLK

(input)

SDIN

(input)

SDOUT

(output)

MSB

MSB-1

sckh

sckl

lcks

lckd

Figure 1. Non-TDM Slave Mode Timing

Figure 2. TDM Slave Mode Timing

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