CS8421

10

DS641PP1

2.

TYPICAL CONNECTION DIAGRAMS

CS8421

VD

VL

Serial

Audio

Source

ILRCK

ISCLK

SDIN

BYPASS

+2.5 V

+3.3 V or +5.0 V

0.1

µF0.1 µF

Serial

Audio

Input

Device

OLRCK

OSCLK

SDOUT

XTI

XTO

RST

SRC_UNLOCK

SAOF

TDM_IN

Hardware Control

Settings

Crystal /Clock

Source

GND

SAIF

MS_SEL

GND

MCLK_OUT

To external

hardware

47 k

Ω

*

**

Figure 5. Typical Connection Diagram, Master and Slave Modes

* The connection (VL or GND) and value of these three resistors determines the mode of operation for the

input and output serial ports as described in Table 1, “Serial Audio Port Master/Slave and Clock Ratio Se-

lect Startup Options (MS_SEL)", Table 2, “Serial Audio Input Port Startup Options (SAIF)", and Table 3,

“Serial Audio Output Port Startup Options (SAOF)", all on page 13.

** MCLK_OUT pin should be pulled high through a 47 k

Ω resistor if an MCLK output is not needed.