CS8421

18

DS641PP1

6.8

Time Division Multiplexing (TDM) Mode

TDM mode allows several CS8421 to be serially connected together allowing their corresponding SDOUT

data to be multiplexed onto one line for input into a DSP or other TDM capable multichannel device.

The CS8421 can operate in two TDM modes. The first mode consists of all of the CS8421’s output ports

set to slave as shown in Figure 13. The second mode consists of one CS8421 output port set to master

and the remaining CS8421’s output ports set to slave as shown in Figure 14.

The TDM_IN pin is used to input the data while the SDOUT pin is used to output the data. The first

CS8421 in the chain should have its TDM_IN set to GND. Data is transmitted from SDOUT most signifi-

cant bit first on the first OSCLK after an OLRCK transition and is valid on the rising edge of OSCLK.

In TDM slave mode, the number of channels that can by multiplexed to one serial data line depends on

the output sampling rate. For slave mode, OSCLK must operate at N*64*Fso, where N is the number of

CS8421’s connected together. The maximum allowable OSCLK frequency is 24.576 MHz, so for Fso =

48 kHz, N = 8 (16 channels of serial audio data).

In TDM master mode, OSCLK operates at 256*Fso, which is equivalent to N = 4, so a maximum of 8 chan-

nels of digital audio can be multiplexed together. Note that for TDM master mode, MCLK must be at least

256*Fso, where Fso

≤ 96 kHz. OLRCK identifies the start of a new frame. Each time slot is 32-bits wide,

with the valid data sample left justified within the time slot. Valid data lengths are 16, 20, 24 or 32-bits.

Figure 11 and Figure 12 show the interface format for master and slave TDM modes.

Channel6

OLRCK

OSCLK

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

SDOUT/

TDM_IN

Channel1

Channel4

Channel2

Channel5

Channel3

32 clks

32 clks

32 clks

32 clks

32 clks

32 clks

Channel8

LSB

MSB

LSB

MSB

Channel7

32 clks

32 clks

Figure 11. TDM Slave Mode Timing Diagram

Channel6

OLRCK

OSCLK

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

SDOUT/

TDM_IN

Channel1

Channel4

Channel2

Channel5

Channel3

256 clks

32 clks

32 clks

32 clks

32 clks

32 clks

32 clks

Channel8

LSB

MSB

LSB

MSB

Channel7

32 clks

32 clks

Figure 12. TDM Master Mode Timing Diagram