ST92195D datasheet(141/249 Pages) STMICROELECTRONICS

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ST92195C/D - SYNC CONTROLLER

SYNC CONTROLLER (Cont’d)

7.5.1 H/V Polarity Control

Two control bits manage the H/V polarities. HPOL

(SCCS0R.6) manages the HSYNC polarity (a pos-

itive polarity assumes the leading edge is the ris-

ing one). VPOL (SCCS0R.7) controls the VSYNC

polarity.

7.5.2 Field Detection

Field detection is necessary information for the

Display controller for fringe and rounding features.

To determine correctly the field in case of using

separate H and V input signals, it is necessary to

provide an internal compensation of the hardware

delay generated on VSYNC (VSYNC is generally

issued by integrating the equalization pulses).

Therefore the VSYNC leading edge is compared

to the leading edge of an internally delayed

HSYNC.

The delay applied to HSYNC is software program-

mable through the SCCS0R (3:0) bits (from 0 to 63

µs). It must be calculated by the user as being the

time constant (modulo 64 µs) used to extract

VSYNC by the other components of the chassis.

7.5.3 Interrupt Generation

The SYNC Controller unit can provide two different

interrupts to the ST9+ Core. The first interrupt ap-

pears at each beginning of field upon detection of

the Vertical Sync pulse coming from the deflection

circuitry (i.e. from VSYNC); it is called the “Field

start” interrupt. A flag is associated to this inter-

rupt, called “FLDST” (SCCS1R.6). This flag is set

to “1” by hardware when the Vertical Sync pulse

appears. It must be cleared by software.

The second interrupt appears at the end of each

Vertical Blank Interval. It is generated at the begin-

ning of the line 25 counted from the deflection cir-

cuitry (i.e. from VSYNC); and is called the “End OF

VBI” interrupt. A flag is associated to this interrupt,

called “EOFVBI” (SCCS1R.7). This flag is set to

“1” by hardware when the line 25 starts. It must be

cleared by software.

These two interrupts EOFVBI and FLDST are re-

spectively attached to the INT4 and INT5 external

interrupt inputs of the ST9+ Core. The leading

edges of the 2 interrupt requests are the falling

ones. (For more details, refer to the Interrupts

chapter).

7.5.4 Sync Controller Working Modes

Different working modes are available fully control-

led by software.

The first two working modes assume that TV de-

flection sync signals are available and stable.

The last two modes assume that no TV signal is

available. The chip works in a free-running mode

providing standard TV Sync signals based on the

main internal 4 MHz clock.

Switching from one mode to any other is done un-

der full software control, through the programming

of two control bits called as MOD1 and MOD0.

These control bits are described in the SCCS1R

7.5.4.1 Standard Sync Input Mode

This mode is accessed when both MOD1 and

MOD0 bits are reset.

In this mode, the µP receives the chassis synchro

through two separate inputs. These are VSYNC

and

HSYNC.

also

assumes

the

VSEP

(SCCS0R.5) is reset.

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