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L6983 数据表(PDF) 28 Page - STMicroelectronics |
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L6983 数据表(HTML) 28 Page - STMicroelectronics |
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28 / 63 page ![]() fPLF= 1 2∙π∙RO∙CC (19) fPHF= 1 2∙π∙RO∙CO (20) Whereas the zero is defined as: fZ= 1 2∙π∙RC∙CC (21) 7.3 Voltage divider The contribution of a simple voltage divider is: GDIVs = R2R1+R2 (22) A small signal capacitor in parallel to the upper resistor (only for the adjustable part number) of the voltage divider implements a leading network (fZERO < fPOLE), sometimes necessary to improve the system phase margin: Figure 25. Leading network example PGOOD BOOT SW SW VBIAS VOUT/FB PGND PGND VIN VIN VINLDO EN/CLKIN FSW VCC A GND A GND E.P. L6983 VOUT GND GND VIN RFSW CVCC CBOOT RPGOOD L R1 R2 COUT CIN CR1 CFILT RFILT Laplace transformer of the leading network: GDIVs = R2R1+R2∙ 1+s∙R1∙CR1 1+s∙ R1∙R2 R1+R2∙CR1 (23) where: fZ= 1 2∙π∙R1∙CR1 (24) fP= 1 2∙π∙ R1∙R2 R1+R2∙CR1 (25) fZ<fP (26) So closing the loop, the loop gain is: Gs =GDIVs ∙GCOs ∙AOs (27) L6983 Voltage divider DS13116 - Rev 1 page 28/63 |
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