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L6983 数据表(PDF) 4 Page - STMicroelectronics |
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L6983 数据表(HTML) 4 Page - STMicroelectronics |
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4 / 63 page ![]() 2 Pin configuration Figure 2. Pin connection (top through view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 E.P. VIN VINLDO AGND EN/CLKIN VCC AGND BOOT VIN Table 1. Pin description Pin Symbol Function 1 VIN DC input voltage. 2 VINLDO DC input voltage connected to the supply rail with a simple RC filter. 3 AGND Analog ground. 4 EN / CLKIN Enable pin with internal voltage divider. Pull-down/up to disable/ enable the device. In LNM versions, this pin is also used to provide an external clock signal, which synchronizes the device. 5 PGOOD The PGOOD open collector output is driven to low impedance when the output voltage is out of regulation and released once the output voltage becomes valid. 6 VBIAS Typically connected to the regulated output voltage, an external voltage source can be used to supply part of the analog circuitry to reduce current consumptions at light load. Connect it to AGND if not used. 7 FB/VOUT This pin operates as VOUT or FB according to the selected part number. In fixed output voltage versions, VOUT is the output voltage sensing with selected internal voltage divider. In adjustable versions, FB is output voltage sensing with eternal voltage divider. 8 FSW Connect an external resistor to program the oscillator frequency and enable the optional dithering. 9 VCC This pin supplies the embedded analog circuitry. Connect a ceramic capacitor (≥ 1 µF) to filter internal voltage reference. 10 AGND Analog ground. 11 BOOT Connect an external capacitor (100 nF typ.) between BOOT and SW pins. The gate charge required to drive the internal NMOS is refreshed during the low-side switch conduction time. L6983 Pin configuration DS13116 - Rev 1 page 4/63 |
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