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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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STM32F479 数据表(PDF) 17 Page - STMicroelectronics |
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STM32F479 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 91 page  DocID029237 Rev 2 17/91 AN4861 Overview of LTDC controller and STM32 MCUs graphical portfolio 89 Figure 9. LTDC AHB master in STM32F429/439 and STM32F469/479 lines smart architecture 1. SRAM1 size = 112 Kbyte for STM32F429/439 and 160 Kbyte for STM32F469/479 2. SRAM2 size = 16 Kbyte for STM32F429/439 and 32 Kbyte for STM32F469/479 3. SRAM3 size = 64 Kbyte for STM32F429/439 and 128 Kbyte for STM32F469/479 4. Dual Quad-SPI interface is only available for STM32F469/479 System architecture on STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 The system architecture of the STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 lines consists mainly of 32-bit multilayer AHB bus matrix that interconnects twelve masters and eight slaves. The LTDC is one of the twelve AHB masters on the AHB busmatrix. The LTDC can autonomously access all the memory slaves on the AHB bus matrix, such as FLASH, SRAM1, SRAM2, FMC or Quad-SPI enabling an efficient data transfer which is ideal for graphical applications. Figure 10 shows the LTDC interconnection in the STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 systems. |
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