STM32F479 datasheet(35/91 Pages) STMICROELECTRONICS

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Creating a graphical application with LTDC

The pixel clock for a specific refresh rate calculated with the following formula:

LCD_CLK (MHz) = total screen size x refresh rate

Where total screen size = total width x total height.

LTDC required bandwidth

The LTDC required bandwidth depends mainly on three factors:

•

The number of used LTDC layers

•

The LTDC layer color depth

•

The pixel clock (depends on the resolution of the display panel and on the refresh rate)

The maximum required bandwidth can be calculated as described below:

•

If only one LTDC layer is used

–

LTDC required bandwidth = LCD_CLK x BppL1

•

If two LTDC layers are used

–

LTDC required bandwidth = LCD_CLK x (BppL1 + BppL2)

Where BppL1 and BppL2 are respectively the color depth for LTDC Layer1 and Layer2.

The LTDC required bandwidth should not exceed the memory's available bandwidth,

otherwise, display problems will occur and the FIFO underrun flag will be set (if the FIFO

underrun interrupt was enabled).

Note:

If the memory used to store the framebuffer is also used for other application purposes, it

may impact the graphical performances of the system.

Check if the used display resolution fits the hardware configuration

The general method for checking whether a display size with a particular color depth is

compatible with memory bandwidth is:

Compute the pixel clock according to the display size or extract it from the display’s

datasheet.

Check if the display’s pixel clock does not exceed the maximum system's supported

pixel clock described in Table 10 or Table 11. The user should use the following

parameters to extract from Table 10 or Table 11 the maximum supported pixel clock

corresponding to the used hardware configuration:

Number of used LTDC layers.

The used system’s clock speed HCLK and framebuffer memory speed.

External framebuffer memory bus width.

Number of AHB masters accessing concurrently to external framebuffer memory.

The user should perform some tests to confirm the hardware compatibility with the

desired display size and color depth. In order to do it, the user should monitor the LTDC

FIFO underrun interrupt flag in the LTDC_ISR register.

If the FIFO underrun interrupt flag is always reset then the user confirms that the

desired display size is compatible with the hardware configuration.

If the FIFO underrun flag is set, the user should check the following points:

Verify if he extracted, from Table 10 or Table 11, the correct maximum pixel clock

corresponding to the right hardware (for example the user is working with a 16-bit

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