STM32F479 datasheet(42/91 Pages) STMICROELECTRONICS

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Creating a graphical application with LTDC

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4.4.2

LTDC and DMA2D/CPU synchronization

When only one framebuffer is used, there is a risk that the framebuffer computation is

displayed on the screen. Multiple buffering techniques such as the double buffering are

commonly used to avoid displaying the framebuffer calculation on the screen.

Even when using a double buffering technique, a tearing effect may appear due to a non-

synchronization between the LTDC and the framebuffer update (either by the CPU or the

DMA2D). A way to solve this issue is the use of the VSYNC signal to synchronize the

workflow of these two masters (LTDC and either CPU or DMA2D).

The LTDC fetches the graphical data from a buffer (called frontbuffer) while the DMA2D

prepares the next frame in another buffer (called backbuffer). The VSYNC period indicates

the end of the actual frame display and that the two buffers should be flipped.

Figure 23. Double buffering: synchronizing LTDC with DMA2D or CPU

The LTDC provides different options to synchronize this workflow:

•

Program the line interruption with the value of the last screen line, the interrupt handler

should flip the framebuffers and start the next framebuffer calculation.

•

Program the shadow reload register (LTDC_SRCR) to Vertical blanking reload to

change the LTDC framebuffer address on the VSYNC period and Poll on VSYNC bit of

the LTDC_CDSR register to unblock the DMA2D.

4.5

Graphic performance optimization

As previously stated in this document, the framebuffer memory bandwidth is the most

important parameter for a graphic application. This section provides some

recommendations to optimize the graphic performances based on bandwidth optimizations

of the framebuffer memory.

4.5.1

Memory allocation

The smart architecture of the STM32 MCUs enables a significant system performance gain

when using the internal SRAM memory split into two or more slaves.

Splitting up the slave memories between masters helps to decrease the competition

between them when they access simultaneously the same SRAM. This action also creates

an additional system bus bandwidth.

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