STM32F479 datasheet(33/91 Pages) STMICROELECTRONICS

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Creating a graphical application with LTDC

Using the internal SRAM instead of an external SRAM or SDRAM has many advantages:

•

Provides a higher throughput (0 wait state access).

•

Reduces the number of required pins and the PCB design complexity.

•

Reduces the BOM, hence the cost, since no external memory is needed.

The only limitation when using the internal SRAM is its limited size (hundreds of Kilobytes).

When the framebuffer size exceeds the available memory, the external SDRAM or SRAM

(driven by the FMC interface) should be used. However, when dealing with external

memories, the user must be careful to avoid bandwidth limitation. For more detailed

information refer to Section 4.5: Graphic performance optimization.

Note:

The color look-up table CLUT can be used to decrease the required framebuffer size. (For

more details refer to the relevant STM32 MCU reference manual).

4.2.2

Checking display compatibility considering the memory

bandwidth requirements

The scope of this section is to explain how to check a display compatibility considering the

framebuffer memory bandwidth. For that, this section describes some important bandwidth

aspects and explains how to determine the required bandwidth for the pixel clock and the

LTDC. Finally, this section shows a simple method that allows to conclude whether a

desired display size is compatible with a specific hardware configuration.

Framebuffer memory bandwidth aspects

Once that the framebuffer location is fixed (either in internal or external memory), the user

should check if its bandwidth can sustain the hardware configuration.

In order to check if the memory bandwidth can sustain the LTDC required bandwidth, the

user must consider any other concurrent accesses to the memory.

In general, a small size framebuffer located in the internal RAM does not require a high

bandwidth. This is because a small size framebuffer means low pixel clock, hence low LTDC

required bandwidth.

A more complex use case to analyze is when the framebuffer is located in an external

memory (SDRAM or SRAM).

Framebuffer memory bus concurrency

•

LTDC, DMA2D and CPU masters

In a typical graphic application where an external SDRAM or SRAM memory is used as

framebuffer, two or three main AHB masters concurrently use the same memory.

The DMA2D (or the CPU) updates the next image to be displayed while the LTDC fetches

and displays the actual image. The memory bus load depends mainly on the LTDC required

bandwidth.

•

Other AHB masters

It is common that an external SDRAM or SRAM memory is shared by other masters and not

only by those used for graphics. This concurrency leads to heavy bus load and may impact

the graphic performances.

Figure 21 shows all the AHB masters with concurrent access to the SDRAM.

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