XT
April 1999
4.5.99
11
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,62
Table 10: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are
± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX.
UNITS
Overall
66.67
182
Clock Skew, Maximum;
SDRAM_0 to any SDRAM pin *
tskw
Measured on the rising edge at 1.5V;
CL = 20pF
100
228
ps
66.67
3.7
tPLH(min)
Measured on the rising edge at 1.5V;
CL = 20pF
100
3.8
66.67
3.7
tPLH(max)
Measured on the rising edge at 1.5V;
CL = 30pF
100
4.0
66.67
3.9
tPHL(min)
Measured on the rising edge at 1.5V;
CL = 20pF
100
3.8
66.67
4.2
Propagation Delay, Average;
CLK_IN to any SDRAM pin *
tPHL(max)
Measured on the rising edge at 1.5V;
CL = 30pF
100
4.0
ns
Clock Outputs (SDRAM_0:17 3.3V Type 4 Clock Buffer)
66.67
1.0
tr(min)
VO = 0.4V to 2.4V; CL = 20pF
100
0.9
66.67
1.2
Rise Time *
tr(max)
VO = 0.4V to 2.4V; CL = 30pF
100
1.0
ns
66.67
1.0
tf(min)
VO = 2.4V to 0.4V; CL = 20pF
100
0.7
66.67
1.1
Fall Time *
tf(max)
VO = 2.4V to 0.4V; CL = 30pF
100
0.8
ns
66.67
6.5
tKH(min)
VO = 2.4V; CL = 20pF
100
3.8
66.67
6.5
Clock High Time *
tKH(max)
VO = 2.4V; CL = 30pF
100
3.8
ns
66.67
6.5
tKL(min)
VO = 0.4V; CL = 20pF
100
4.6
66.67
6.3
Clock Low Time *
tKL(max)
VO = 0.4V; CL = 30pF
100
4.5
ns
66.67
49
From rising edge to rising edge at
1.5V; CL = 20pF
100
45
66.67
50
Duty Cycle *
From rising edge to rising edge at
1.5V; CL = 30pF
100
46
%
tPZL
4.7
Tristate Enable Delay *
tPZH
Output tristated to output active; CL = 20pF
4.6
ns
tPLZ
6.3
Tristate Disable Delay *
tPHZ
Output active to output tristated; CL = 20pF
7.9
ns
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