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XT
April 1999
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3.0
Programming Information
Table 2: Clock Enable
CONTROL INPUTS
CLOCK OUTPUTS (MHz)
OE
SDRAM_0:17
0tristate
1
CLK_IN
3.1
Power-Up Initialization
All outputs are enabled and active upon power-up, and all
output control register bits are initialized to one.
The outputs must be configured at power-up and are not
expected to be configured during normal operation. Inac-
tive outputs are held low and are disabled from switching.
3.1.1
Unused Outputs
Outputs that are not used in versions of this device with a
reduced pinout are still operational internally. To reduce
power dissipation and crosstalk effects from the unloaded
outputs, it is recommended that these outputs be shut off
via the Control Registers.
3.2
Register Programming
A logic-one written to a valid bit location turns on the as-
signed output clock. Likewise, a logic-zero written to a
valid bit location turns off the assigned output clock.
Any unused or reserved register bits should be cleared to
zero.
Serial bits are written to this device in the order shown in
Table 3.
Table 3: Register Summary
SERIAL BIT
DATA BYTE
CLOCK OUTPUT
0
(MSB)
SDRAM_7
1
SDRAM_6
2
SDRAM_5
3
SDRAM_4
4
SDRAM_3
5
SDRAM_2
6
Byte 0
SDRAM Control Register 0
SDRAM_1
7
(LSB)
SDRAM_0
8
(MSB)
SDRAM_15
9
SDRAM_14
10
SDRAM_13
11
SDRAM_12
12
SDRAM_11
13
SDRAM_10
14
Byte 1
SDRAM Control Register 1
SDRAM_9
15
(LSB)
SDRAM_8
16
(MSB)
SDRAM_17
17
SDRAM_16
18
Reserved
19
Reserved
20
Reserved
21
Reserved
22
Byte 2
SDRAM Control Register 2
Reserved
23
(LSB)
Reserved
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