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XT
April 1999
4.5.99
7
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Figure 6: Random Register Write Procedure (I
2C-bus)
A
A
DATA
W A
From bus host
to device
S
REGISTER ADDRESS
P
From device
to bus host
DEVICE ADDRESS
Register Address
Acknowledge
STOP Condition
Data
Acknowledge
Acknowledge
START
Command
WRITE Command
7-bit Receive
Device Address
Figure 7: Random Register Read Procedure (I
2C-bus)
A
R
A
A
A
W
S
REGISTER ADDRESS
P
S
DEVICE ADDRESS
START
Command
WRITE Command
Acknowledge
Register Address
Acknowledge
READ Command
Acknowledge
Data
NO Acknowledge
STOP Condition
From bus host
to device
From device
to bus host
7-bit Receive
Device Address
7-bit Receive
Device Address
DEVICE ADDRESS
DATA
Repeat START
Figure 8: Sequential Register Write Procedure (I
2C-bus)
A
A
A
W
S
P
START
Command
WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Data
Acknowledge
Data
STOP Command
Acknowledge
Acknowledge
From bus host
to device
From device
to bus host
7-bit Receive
Device Address
DEVICE ADDRESS
A
A
REGISTER ADDRESS
DATA
DATA
DATA
Figure 9: Sequential Register Read Procedure (I
2C-bus)
A
W
S
START
Command
WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Acknowledge
Data
STOP Command
Acknowledge
READ Command
NO Acknowledge
From bus host
to device
From device
to bus host
7-bit Receive
Device Address
7-bit Receive
Device Address
DEVICE ADDRESS
A
A
REGISTER ADDRESS
A
R
A P
S
DEVICE ADDRESS
DATA
DATA
Repeat START
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