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XT
April 1999
4.5.99
13
)6)6)6)6
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,62
Figure 14: SDRAM_0:17 Clock Output (3.3V Type 4 Clock Buffer)
Low Drive Current (mA)
High Drive Current (mA)
Voltage
(V)
MIN.
TYP.
MAX.
Voltage
(V)
MIN.
TYP.
MAX.
0
0
0
0
0
-72
-116
-198
0.4
23
34
53
1
-72
-116
-198
0.65
35
52
83
1.4
-68
-110
-188
0.85
43
65
104
1.5
-67
-107
-184
1
49
74
118
1.65
-64
-103
-177
1.4
61
93
152
1.8
-60
-98
-170
1.5
64
98
159
2
-54
-90
-157
1.65
67
103
168
2.4
-39
-69
-126
1.8
70
108
177
2.6
-30
-56
-107
1.95
72
112
184
3.135
0
-15
-46
3.135
72
112
204
3.3
0
-23
3.6
112
204
3.465
0
-220
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
200
220
00.5
11.5
22.5
33.5
4
PÃWyhtrÃW
P
Ã8
r
Ã
6
MIN.
TYP.
MAX.
30 Ω
50 Ω
90 Ω
Figure 15: DC Measurement Points
V
IH 3.3 = 2.0V
V
IL 3.3 = 0.8V
V
OL 3.3 = 0.4V
V
OH 3.3 = 2.4V
1.5V
3.3V
(device
interface)
(system
interface)
Figure 16: Clock Skew Measurement Point
t
skw
3.3V
3.3V
1.5V
1.5V
Figure 17: Timing Measurement Points
t
KH
t
r
Duty Cycle
t
KL
τ
KP
2.4V
1.5V
0.4V
t
f
t
PLZ
V
OL
V
OH
V
SS
V
DD
10%
90%
t
PHZ
50%
50%
50%
50%
t
PZL
t
PHZ
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