XT
April 1999
4.5.99
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For an I
2C-bus interface, the device can support two de-
vice addresses to permit multiple devices on one I
2C-bus.
The A2 address bit is ignored and can be set to either a
one or a zero.
Therefore, for an I
2C-bus interface the device address is:
A6
A5
A4
A3
A2
A1
A0
101
1
X
00
4.2.2
I
2C-bus: Random Register Write Procedure
Random write operations, as shown in Figure
6, allow the master to directly write to any
register. To initiate a write procedure, the R/W
bit that is transmitted after the seven-bit I
2C
device address is a logic-low. This indicates to the ad-
dressed slave device that a register address will follow
after the slave device acknowledges its device address.
The register address is written into the slave’s address
pointer. Following an acknowledge by the slave, the
master is allowed to write eight bits of data into the ad-
dressed register. A final acknowledge is returned by the
device, and the master generates a STOP condition.
If either a STOP or a repeated START condition occurs
during a Register Write, the data that has been trans-
ferred is ignored.
4.2.3
I
2C-bus: Random Register Read Procedure
Random read operations allow the master to directly read
from any register. To perform a read procedure, as
shown in Figure 7, the R/W bit that is transmitted after the
seven-bit I
2C address is a logic-low, as in the Register
Write procedure. This indicates to the addressed slave
device that a register address will follow after the slave
device acknowledges its device address. The register
address is then written into the slave’s address pointer.
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave address is
then resent, with the R/W bit set this time to a logic-high,
indicating to the slave that data will be read. The slave
will acknowledge the device address, and then transmits
the eight-bit word. The master does not acknowledge the
transfer but does generate a STOP condition.
4.2.4
I
2C-bus: Sequential Register Write Procedure
Sequential write operations, as shown in Figure 8, allow
the master to write to each register in order. The register
pointer is automatically incremented after each write. This
procedure is more efficient than the Random Register
Write if several registers must be written.
To initiate a write procedure, the R/W bit that is transmit-
ted after the seven-bit I
2C device address is a logic-low.
This indicates to the addressed slave device that a reg-
ister address will follow after the slave device acknowl-
edges its device address. The register address is written
into the slave’s address pointer. Following an acknowl-
edge by the slave, the master is allowed to write data up
to the last addressed register before the register address
pointer overflows back to the beginning address. An ac-
knowledge by the device between each byte of data must
occur before the next data byte is sent.
Registers are updated every time the device sends an
acknowledge to the host. The register update does not
wait for the STOP condition to occur. Registers are
therefore updated at different times during a Sequential
Register Write.
4.2.5
I
2C-bus: Sequential Register Read Procedure
Sequential read operations allow the master to read from
each register in order. The register pointer is automati-
cally incremented by one after each read. This proce-
dure, as shown in Figure 9, is more efficient than the
Random Register Read if several registers must be read
from.
To perform a read procedure, the R/W bit that is trans-
mitted after the seven-bit I
2C address is a logic-low, as in
the Register Write procedure. This indicates to the ad-
dressed slave device that a register address will follow
after the slave device acknowledges its device address.
The register address is then written into the slave’s ad-
dress pointer.
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave address is
then resent, with the R/W bit set this time to a logic-high,
indicating to the slave that data will be read. The slave
will acknowledge the device address, and then transmits
all data starting with the initial addressed register. The
register address pointer will overflow if the initial register
address is larger than zero. After the last byte of data, the
master does not acknowledge the transfer but does gen-
erate a STOP condition.
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