IS25LP032D-RBLE:P datasheet(44/118 Pages) ISSI

44 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.7 FAST READ QUAD I/O OPERATION (FRQIO, EBh)

The FRQIO instruction allows the address bits to be input four bits at a time. This may allow for code to be executed

directly from the SPI in some applications.

A Quad Enable (QE) bit of Status Register must be set to "1" before sending the Fast Read Quad I/O instruction.

The FRQIO instruction code is followed by three address bytes (A23

– A0) and dummy cycles (configurable, default

is 6 clocks), transmitted via the IO3, IO2, IO1 and IO0 lines, with each group of four bits latched-in during the rising

edge of SCK. The address of MSB inputs on IO3, the next bit on IO2, the next bit on IO1, the next bit on IO0, and

continue to shift in alternating on the four. Depending on the usage of AX read operation mode, a mode byte may

be located after address input.

The first data byte addressed is shifted out on the IO3, IO2, IO1 and IO0 lines, with each group of four bits shifted

out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is output on IO3, while

simultaneously the second bit is output on IO2, the third bit is output on IO1, etc. Figure 8.8 illustrates the timing

sequence.

The first byte addressed can be at any memory location. The address is automatically incremented after each byte

of data is shifted out. When the highest address is reached, the address counter will roll over to the 000000h

address, allowing the entire memory to be read with a single FRQIO instruction. FRQIO instruction is terminated

by driving CE# high (VIH).

The device supports the AX read operation by applying mode bits during dummy period. Mode bits consist of 8

bits, such as M7 to M0. Two cycles after address input are reserved for Mode bits in FRQIO execution. M7 to M4

are important for enabling this mode. M3 to M0 become don’t care for future use. When M[7:4]=1010(Ah), it enables

the AX read operation and subsequent FRQIO execution skips command code. It saves cycles as described in

Figure 8.9. When the code is different from AXh (

where X is don’t care), the device exits the AX read operation.

After finishing the read operation, device becomes ready to receive a new command. SPI or QPI mode configuration

retains the prior setting. Mode bit must be applied during dummy cycles. Number of dummy cycles in Table 6.11

includes number of mode bit cycles. If dummy cycles are configured as 6 cycles, data output will start right after

mode bits and 4 additional dummy cycles are applied.

If the FRQIO instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is

ignored and will not have any effects on the current cycle.

IS25LP032D-RBLE:P 数据表(PDF) 44 Page - Integrated Silicon Solution, Inc

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