PRELIMINARY
CY28344
Document #: 38-07113, Rev. *A
Page 4 of 22
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc. can be individually enabled or
disabled.
The registers associated with the Serial Data Interface
initializes to it’s default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte Write, byte Read,
block Write and block Read operation from the controller. For
block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte Write and byte Read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code, as
described in Table 1.
The block Write and block Read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte Write and byte
Read protocol.
The slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit
Descriptions
7
0 = Block Read or block Write operation
1 = Byte Read or byte Write operation
6:0
Byte offset for byte Read or byte Write operation. For block Read or block Write operations,
these bits should be “0000000”
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address – 7 bit
2:8
Slave address – 7 bit
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bit
“00000000” stands for block operation
11:18
Command Code – 8 bit
“00000000” stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte Count – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29:36
Data byte 0 – 8 bits
28
Read
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 1 – 8 bits
30:37
Byte count from slave – 8 bits
46
Acknowledge from slave
38
Acknowledge
...
Data Byte N/Slave Acknowledge...
39:46
Data byte from slave – 8 bits
...
Data Byte N – 8 bits
47
Acknowledge
...
Acknowledge from slave
48:55
Data byte from slave – 8 bits
...
Stop
56
Acknowledge
...
Data bytes from slave/acknowledge
...
Data byte N from slave – 8 bits
...
Not acknowledge
...
Stop
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