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CY28344PVC 数据表(PDF) 5 Page - Cypress Semiconductor

部件名 CY28344PVC
功能描述  FTG for Intel Pentium 4 CPU and Chipsets
PDF  22 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY28344PVC 数据表(HTML) 5 Page - Cypress Semiconductor

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PRELIMINARY
CY28344
Document #: 38-07113, Rev. *A
Page 5 of 22
Data Byte Configuration Map
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address – 7 bit
2:8
Slave address – 7 bit
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bit
“1xxxxxxx” stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
11:18
Command Code – 8 bit
“1xxxxxxx” stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Data byte – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29
Stop
28
Read
29
Acknowledge from slave
30:37
Data byte from slave – 8 bits
38
Not acknowledge
39
Stop
Data Byte 0
Bit
Pin#
Name
Description
Power On
Default
Bit 7
--
SEL3
SW Frequency selection bits. See Table 4.0
Bit 6
--
SEL2
0
Bit 5
--
SEL1
0
Bit 4
--
SEL0
0
Bit 3
--
FS_Override
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
0
Bit 2
--
SEL4
SW Frequency selection bits. See Table 4.0
Bit 1
--
Spread Spectrum Enable
0 = OFF; 1 = Enabled
0
Bit 0
--
Reserved
Reserved
0
Data Byte 1
Bit
Pin#
Name
Description
Power On
Default
Bit 7
40, 39
CPU2, CPU2#
(Active/Inactive)
1
Bit 6
44, 43
CPU1, CPU1#
(Active/Inactive)
1
Bit 5
47, 46
CPU0, CPU0#
(Active/Inactive)
1
Bit 4
--
Latched FS4 input
Latched FS[4:0] inputs. These bits are Read-only.
X
Bit 3
--
Latched FS3 input
X
Bit 2
--
Latched FS2 input
X
Bit 1
--
Latched FS1 input
X
Bit 0
--
Latched FS0 input
X



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