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HCS473-SLROM 数据表(PDF) 14 Page - Microchip Technology |
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HCS473-SLROM 数据表(HTML) 14 Page - Microchip Technology |
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14 / 68 page ![]() HCS473 DS40035C-page 12 Preliminary 2002 Microchip Technology Inc. FIGURE 3-1: GENERAL CODE WORD FORMAT FIGURE 3-2: CODE WORD ORGANIZATION Preamble Header Guard Time Data Bits S2 S1 S0 S3 Synchronization Counter Synchronization Counter LSb V LOW 1-Bit Fixed Code Portion (35 Bits) CRC 2 Bits V LOW 1-Bit SER 1 Most Sig 16 Bits SER 0 Least Sig 16 Bits BUT 4 Bits DISCRIM 8 Bits 20 Bits 20 0 Hopping Code Portion Message (32 Bits) C1 C0 MSb 67 Data bits Transmitted LSb first. Hopping Code: Fixed Code Portion (37 Bits) QUE 2 Bits CRC 2 Bits BUT 4 Bits S2 S1 S0 S3 SER 0 Least Sig16 Bits BUT 4 Bits Counter Overflow 2 Bits DISCRIM 10 Bits Synchronization 16 Bits Counter 15 0 S2 S1 S0 S3 OVR1 OVR0 Hopping Code Portion Message (32 Bits) Q1 Q0 C1 C0 MSb LSb 69 Data bits Transmitted LSb first. SER 1 12 MSb’s Hopping Code: CRC 2 Bits V LOW 1-Bit BUT 4 Bits SDVAL3 12 Most Sig Bits 111 1 SDVAL2 16 Bits SDVAL1 16 Bits SDVAL0 16 Least Sig Bits C1 C0 LSb MSb Shaded 65 bits included in CRC calculation 69 Data bits Transmitted LSb first. Fixed Code Portion (9 Bits) Seed Value (60 Bits) Seed Code: 20-bit Synchronization Counter (CNTSEL=1) 16-bit Synchronization Counter (CNTSEL=0) 32-bit Serial Number (XSER = 1) 28-bit Serial Number (XSER = 0) Button Queuing enabled (QUEN=1) Button Queuing disabled (QUEN=0) Queuing enabled (QUE = 1) S2 S1 S0 S3 QUE 2 Bits Q1 Q0 |
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