TPS7A0233DBVR datasheet(20/43 Pages) TI

20 / 43 page

VOUT(NOM)

0 V

0 mA

VOUT

VFOLDBACK

ICL

ISC

IRATED

IOUT

Brickwall

Foldback

TPS7A02

SBVS277B – JULY 2019 – REVISED MARCH 2020

www.ti.com

Submit Documentation Feedback

Feature Description (continued)

7.3.6 Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a

brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the

output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the

voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output

voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-

circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.

For this device, VFOLDBACK = 0.5 V.

The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in brickwall current

limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output

is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the

device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If

the output current fault condition continues, the device cycles between current limit and thermal shutdown. For

more information on current limits, see the Know Your Limits application report.

Figure 57 shows a diagram of the foldback current limit.

Figure 57. Foldback Current Limit

7.3.7 Undervoltage Lockout (UVLO)

The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a

controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input

drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.

7.3.8 Thermal Shutdown

The device contains a thermal shutdown protection circuit to disable the device when the junction temperature

(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device

resets (turns on) when the temperature falls to TSD(reset) (typical).

TPS7A0233DBVR 数据表(PDF) 20 Page - Texas Instruments

TPS7A0233DBVR 数据表(HTML) 20 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

数据表下载