C

UVLO Rising Threshold

UVLO Hysteresis

24

TPS7A02

SBVS277B – JULY 2019 – REVISED MARCH 2020

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Application Information (continued)

During transitions from a heavy load to a light load, the:

•

Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to

increase (region F)

•

Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load

discharging the output capacitor (region G)

A larger output capacitance reduces the peaks during a load transient but slows down the response time of the

device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher

current discharge path is provided for the output capacitor.

8.1.4 Undervoltage Lockout (UVLO) Operation

The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational

voltage range, and ensures that the device shuts down when the input supply collapses. Figure 59 shows the

UVLO circuit response to various input voltage events. The diagram can be separated into the following parts:

•

Region A: The device does not start until the input reaches the UVLO rising threshold.

•

Region B: Normal operation, regulating device.

•

Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The

output may fall out of regulation but the device remains enabled.

•

Region D: Normal operation, regulating device.

•

Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the

output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising

threshold is reached by the input voltage and a normal start-up follows.

•

Region F: Normal operation followed by the input falling to the UVLO falling threshold.

•

Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The

output falls because of the load and active discharge circuit.

Figure 59. Typical UVLO Operation

Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit

on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator

must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage

(2)

Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system

voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low

dropout of the TPS7A02 allows for maximum efficiency across a wide range of output voltages.

The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal

pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that

conduct heat to any inner plane areas or to a bottom-side copper plane.