ADP1074ACCZ-R7 datasheet(18/32 Pages) AD

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ADP1074

Data Sheet

Rev. D | Page 18 of 32

PRIMARY SIDE SUPPLY, INPUT VOLTAGE, AND LDO

Two pins on the primary side are supply pins: VIN and

VREG1. A high voltage LDO regulator connected to VIN has a

regulated output of 8 V at the VREG1 pin. This LDO regulator

provides power to the internal bias circuitry, primary side

iCouplers and housekeeping circuits, and the primary

MOSFET drivers at the NGATE and PGATE pins.

To reduce power consumption in the LDO for input voltages

higher than approximately 30 V, an auxiliary winding on the

transformer of the active clamp forward topology can be used

to power VREG1. This auxiliary supply voltage must be higher

than the regulated output at VREG1 so that the LDO shuts off

during normal operation. The recommended auxiliary voltage

is ≥8.5 V and ≤13 V because an internal 14 V Zener diode is

connected at VREG1.

For a high input voltage application to avoid losses in the LDO,

connect the VIN and VREG1 pins together and apply an auxiliary

voltage of 8 V to 10 V, which exceeds the VIN pin UVLO of

typically 4.5 V. Take care that this voltage does not exceed the

internal Zener clamp voltage of 14 V (typical). The typical value

is 10 V.

SECONDARY SIDE SUPPLY AND LDO

Two pins on the secondary side are supply pins: VDD2 and

VREG2.

The secondary side is typically powered by the output rail of the

converter by connecting it to the VDD2 pin. The UVLO for the

secondary side is typically 3.5 V, at which the secondary side

starts up. For output voltages less than the secondary UVLO

voltage, a third winding is required to generate an auxiliary voltage

to power the secondary circuitry. The internal 5 V LDO regulator

at the VREG2 pin powers the MOSFET drivers, secondary side

Couplers, and housekeeping circuits. When VDD2 is less than

5 V, the LDO regulator operates in dropout mode.

For output voltages higher than 24 V, connecting the output

voltage directly to VDD2 can result in significant power

dissipation in the LDO. For instance, at 24 V and with the total

driver current at 10 mA, the power dissipated in the LDO is

0.19 W (10 mA × 19 V). It is recommended to power VDD2

with an auxiliary voltage in the 8 V to 12 V range.

PRECISION ENABLE

The enable threshold at the EN pin is precision voltage referenced

at 1.2 V. Assuming VIN is above the UVLO voltage (typically

4.5 V), the ADP1074 is enabled when the voltage at EN rises above

1.2 V. The crossing of the voltage, such that VEN > 1.2 V,

enables the internal 8 V LDO regulator on the VREG1 pin, and,

after the internal biasing is finished, a soft start procedure is

initiated.

Connect a resistive divider between EN and VIN to set up the

input start-up voltage (see Figure 14.) An internal current source

at EN allows the user to program the UVLO start-up voltage with

a desirable hysteresis. To calculate the start-up voltage with

hysteresis, use the superposition theorem or nodal analysis to

obtain the EN pin voltage, as follows:

(||

)

R1 R2









where:

VEN is the EN pin voltage.

IEN is the current source at the EN pin (1 μA for turn on and

4 μA for turn off).

The user can adjust the R1, R2, and RH resistors such that

VEN ≥ 1.2 V and obtain the desired hysteresis.

An internal 1 μA pull-down current is always on, and the 3 μA

current is active only when the VEN is below the EN threshold

and becomes inactive when VEN is above the EN threshold.

In general, a higher input voltage requires a larger hysteresis. It

is recommended to keep a capacitor on the EN pin to AGND1

to provide a low impedance path that prevents any noise, which

toggles the EN pin when the input voltage hovers at the threshold.

8V LDO

ADP1074

1µA

3µA

LOGIC

VREF

1.2V

VIN

HYSTERESIS

GENERATOR

Figure 14. Precision EN with Adjustable Hysteresis

When the EN pin is less than the EN threshold, the system

enables the soft stop procedure. SR1 and SR2 take up to a

maximum of two switching periods to terminate. See the Soft

Start Procedure section for more details.

SOFT START PROCEDURE

The following procedure assumes that the VDD2 pin is powered

directly from the output voltage of the power supply.

To ensure a smooth output voltage ramp during startup, the

soft start sequence is controlled by two soft start control circuits,

one in the primary (for open-loop soft start, using the SS1 pin)

and the other in the secondary (for closed-loop soft start, using

the SS2 pin). Proper handshaking between the primary side and

the secondary side is needed prior to the secondary side taking

control.

The open-loop soft start time is determined by the capacitor on

the SS1 pin. This pin sources a 9.1 μA constant current that

builds up a voltage on the SS1 pin. The voltage on the SS1 pin is

proportional to the peak primary current limit where 0 V and

1.5 V correspond to a peak current of 0 A and 120 mV/RSENSE,

respectively. This rate is the open-loop soft start. During this

time, the ADP1074 starts firing the PWM pulses, and the

output voltage continues to build up slowly if the average

inductor current limit exceeds the load current. Because the

ADP1074 is a current mode controller, the output capacitor

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